Merge pull request #15172 from brumskysb/docs/div-scale-f64-rdna2

docs(shader): record `v_div_scale_f64` denormal modes on RDNA2

docs/dev/debt/shader.md

@@ -161,7 +161,7 @@
 - [f32 compares in denormal modes 1 and 2](../../../core/shader/recompiler/Translation/src/VectorInstructions.cpp) (`v_cmp_X_f32` and `v_cmpx_X_f32` with X = eq, ge, gt, le, lg, lt, neq, nge, ngt, nle, nlg, nlt) flush their f32 denormal inputs by bit 0 of the `FLOAT_MODE` f32 denormal field: mode 1 keeps them as mode 3 does, and mode 2 flushes them as mode 0 does. Measured on RDNA2 (gfx1030, Radeon RX 6800, AMD Windows driver 32.0.21045.5002 through HIP) over 484 operand pairs of zeros, denormals, minimum normals, ones, the largest finite value, infinities and quiet and signaling NaNs of both signs, in VOPC form, at IEEE=0 and IEEE=1 with each f32 denormal mode 0 to 3, f32 round to nearest even, DX10_CLAMP=1, f16 denormals kept, f16 round to nearest even and FP16_OVFL=0. The PS5's gfx1013 is not measured.
 - [f32 conversions in denormal modes 1 and 2](../../../core/shader/recompiler/Translation/src/VectorInstructions.cpp) (`v_cvt_i32/u32/rpi_i32/flr_i32_f32`, `v_frexp_exp_i32_f32`, `v_cvt_f64_f32`, `v_cvt_pknorm_i16/u16_f32`, `v_cvt_pk_u8_f32`, `v_cvt_pkrtz_f16_f32` and `v_cvt_f16_f32`) flush their f32 denormal inputs by bit 0 of the `FLOAT_MODE` f32 denormal field: mode 1 keeps them as mode 3 does, and mode 2 flushes them as mode 0 does. Measured on RDNA2 (gfx1036, ROCm 7.1.1, Linux 7.2) over 148 sources and 484 operand pairs (zeros, denormals, minimum normals, f16 limits, the largest finite value, infinities, NaNs) at IEEE=0 and IEEE=1 in every f32 denormal and round mode, and for the f16 and f64 results in every f16/f64 denormal and round mode. `v_mad_mixlo/mixhi_f16`, which RDNA2 lacks, still throw in modes 1 and 2. The PS5's gfx1013 is not measured.
 - [v_div_scale_f32 and v_div_fixup_f32 in denormal modes 1 and 2](../../../core/shader/recompiler/Translation/src/VectorInstructions.cpp) throw with a directed f32 round mode, where an underflowing `v_div_fixup_f32` result rounds to the smallest denormal and bit 1 of the `FLOAT_MODE` f32 denormal field flushes it, and in mode 1 `v_div_scale_f32` throws when the module cannot declare `DenormPreserve 32`; the PS5's gfx1013 is not measured. At round to nearest even `v_div_fixup_f32` follows bit 0 (mode 1 as mode 3, mode 2 as mode 0), and `v_div_scale_f32` flushes its inputs in mode 2 as in mode 0 and in mode 1 keeps them and flushes a denormal result to a zero of its sign, with the VCC of mode 3. Measured on RDNA2 (gfx1036, AMD Windows driver 32.0.21030.31 through HIP) over 2,304 rows (24 x 24 operand pairs with src0 the denominator and the numerator, four quotients) at IEEE 0 and 1 in every f32 denormal and round mode.
-- [v_div_scale_f64 in denormal modes 0, 1 and 2](../../../core/shader/recompiler/Translation/src/Float64Instructions.cpp) is not measured on the PS5's gfx1013 or on RDNA2, and directed round modes are not measured; gfx1101 returns an infinity where the recompiler scales the value operand by 2^-128 to a subnormal or zero, a scale-model gap kept separate from the denormal field and left unchanged. It flushes its three inputs to a zero of their sign when bit 0 of the `FLOAT_MODE` f16/f64 denormal field is clear (modes 0, 2) and keeps them when set (1, 3); a flushed denominator or numerator becomes zero, so the default NaN 0xfff8000000000000 results; a denormal result is flushed to a zero of its sign when bit 1 is clear (modes 0, 1) and kept otherwise (2, 3); the VCC is unchanged. IEEE 0 and 1 agree. Measured on RDNA3 (gfx1101, Radeon RX 7700 XT) with the hardware oracle at IEEE=0 and IEEE=1 over 91,136 rows. Shaders without a known float mode keep the previous lowering.
+- [v_div_scale_f64 in denormal modes 0, 1 and 2](../../../core/shader/recompiler/Translation/src/Float64Instructions.cpp) is not measured on the PS5's gfx1013, nor are directed round modes; gfx1101 returns an infinity where the recompiler scales the value by 2^-128 to a subnormal or zero, a scale-model gap left unchanged. It flushes its three inputs to a zero of their sign when bit 0 of the `FLOAT_MODE` f16/f64 denormal field is clear (0, 2) and keeps them when set (1, 3); a flushed src1 or src2 gives the default NaN 0xfff8000000000000, while a flushed src0 alone gives a signed zero, measured on RDNA2 (gfx1036). A denormal result is flushed to a zero of its sign when bit 1 is clear (0, 1) and kept otherwise (2, 3); the VCC is unchanged. IEEE 0 and 1 agree. Measured on RDNA3 (gfx1101, RX 7700 XT) with the hardware oracle at IEEE=0 and 1 over 91,136 rows, and on RDNA2 (gfx1036) over 40 pairs, four arrangements, 2,560 values. Shaders without a known float mode keep the previous lowering.
 - [f16 compares](../../../core/shader/recompiler/Translation/src/CompareInstructions.cpp) (`v_cmp_X_f16` and `v_cmpx_X_f16` with X = eq, ge, gt, le, lg, lt, neq, nge, ngt, nle, nlg, nlt) flush their f16 denormal inputs to a zero of the same sign by bit 0 of the `FLOAT_MODE` f16 denormal field: modes 0 and 2 flush them, 1 and 3 keep them. Measured on RDNA2 (gfx1031, Radeon RX 6700 XT, AMD Windows driver 32.0.21045.5002 through HIP) over 256 operand pairs of zeros, denormals, minimum normals, ones, the largest finite value, infinities and quiet and signaling NaNs of both signs, in VOPC form, at IEEE=0 and IEEE=1 with each f16 denormal mode 0 to 3, f16 round to nearest even, DX10_CLAMP=1, f32 denormals kept and FP16_OVFL=0. Shaders without a known float mode keep the previous lowering. The PS5's gfx1013 is not measured.
 - [DB_SHADER_CONTROL.PRIMITIVE_ORDERED_PIXEL_SHADER](../../../core/shader/recompiler/SpirvBackend/src/SpirvModuleEmitter.cpp) (shader recompiler) - the host pixel interlock spans the whole shader, not only up to `s_sendmsg` ORDERED_PS_DONE.
 - [POPS collision SGPRs](../../../core/shader/recompiler/SpirvBackend/src/SpirvModuleEmitter.cpp) (shader recompiler) - the collision wave ID and intrawave collision mask read 0, so a title skips its POPS wait and runs its per-collision loop once.