232 Commits
Author SHA1 Message Date
Dean 5efe8f6520 Merge pull request #7223 from yabanana/feature/nested-resource-tables
feat(shader): resolve nested image tables through runtime pointers
2026-11-04 16:57:51 +13:00
Dean Galvin 635f569fea Merge main 4f41f4c375 into #7223 (7f36e41c45)
Conflicts resolved:
- libSceAgcDriver CMakeLists.txt: main moved test registration into tests/cmake/<exe>.cmake (tools/agc_test_split.py resolve); this branch's nested image table tests now sit in agc_driver_image_table_tests.cmake, and its nested snapshot retry test sits next to main's descriptor phis test in agc_shader_memory_tests.cmake.
- ResourceMaterializer.cpp: table equality compares both this branch's nested/pointers and main's resourceViews; the footprint counts main's resource views and this branch's pointers.
- ShaderDiskCache.cpp: both sides grew the descriptor source record (this branch: TableColumn::buffer, 1 byte; main: requiredBlocks, an 8-byte count), so the decoder minimum is 72 + 1 + 8 = 81, and the field-count asserts are DescriptorSource 4 and TableColumn 19.
- ShaderDiskCache.hpp: FormatVersion 56, an unclaimed number (main has 52; 53, 54 and 55 are already set by other open PRs).
- ResourceMaterializer.cpp (semantic, no text conflict): main added the per-image resourceViews loop to Snapshot(source, table), and it uses the top-level table index; this branch moved that copying into CopyRecords(), which nested tables share and which has no table index. The loop now runs in Snapshot right after CopyRecords, as on main; nested tables carry no resource views, as before.
2026-11-04 04:43:38 +13:00
fma-rc 80f07b510f fix(recompiler): count the volume gather field next to main's optional descriptor field in the disk cache info encoder 2026-11-03 12:39:01 +01:00
fma-rc a3834314f8 fix(recompiler): pair a 3D gather's state only with its own sampler and keep z half border out of border handling
A 3D sample of the same image through another sampler no longer feeds the gather's
state, z modes 4 and 5 no longer count as border addressing, a null image no
longer divides by a zero extent, and the test covers per-axis modes, rounding
ties, denormals, null images and the vertex stage.
2026-11-03 12:37:05 +01:00
fma-rc e26a9c81ca fix(recompiler): address a 3D gather by the sampler's clamp modes and border color 2026-11-03 12:37:04 +01:00
Dean 66387a10ee Merge pull request #10000 from EagleBearerYS/feat/shader-sampler-limits
feat(shader): raise the sampler and sampled-pair limits past the 32-bit sampler masks
2026-11-03 21:09:43 +13:00
Dean 1f272537eb Merge pull request #12764 from Pipodi/perf/flat-private-aperture-1028
perf(recompiler): back compute scratch with a device buffer slot pool
2026-11-03 11:35:12 +13:00
Dean 906597a512 Merge pull request #12246 from B-Howell/feat/agc-1d-array-layer-rows
feat(agc): sample 1D arrays past maxImageArrayLayers as rows of a 2D image
2026-11-03 02:36:11 +13:00
Yunus Shaikh 760a550294 Merge main into feat/shader-sampler-limits
# Conflicts:
#	core/shader/recompiler/ShaderDiskCache.hpp
2026-11-02 00:48:24 -08:00
Dean Galvin fee187ee67 Merge commit '88e804b0a7df1f1ac373a9e2f72fb378d925fdd4' into HEAD
# Conflicts:
#	core/libs/prx/libSceAgcDriver/Execution/src/VulkanDevice.cpp
#	docs/dev/debt/libSceAgcDriver.md
#	docs/dev/debt/shader.md
2026-11-02 21:17:34 +13:00
Dean d9e14126da Merge pull request #7694 from Ondra97/codex/fix-descriptor-phi
fix(shader): split scalar-address descriptor phis
2026-11-02 20:56:24 +13:00
Alex ColliniandClaude Opus 5.5 a46f050af8 perf(recompiler): back compute scratch with a device buffer slot pool
NVIDIA's front end spends tens of seconds per large compute program on the
dynamically indexed Function arrays that held the per-lane scratch. A compute
program that uses scratch (scratch_* or a FLAT access that the aperture split
routes to the private aperture) now keeps it in a storage buffer instead, so
no Function array is declared or indexed. FLAT routing is unchanged.

The driver allocates one buffer per compute pipeline on its first dispatch,
capped by APS5_SCRATCH_POOL_MIB (default 64), holding a lock word and an
invocation counter per slot followed by the slots, and binds it in descriptor
set 2 (the layout of the device-memory LDS buffer). The shader takes the slot
count from the array length. Invocation 0 of each workgroup claims a slot with
a compare-exchange scan that starts at its linear workgroup id and spins until
it wins one; a barrier publishes the slot. Every invocation decrements the
slot's counter on every compute exit and the last one frees the lock, so
divergent exits and concurrent dispatches of one pipeline share the buffer
safely. The emitter fails the compile if a compute return lacks the release.
Programs without scratch keep their SPIR-V and pipeline layout.

The buffer is decorated Coherent: without it NVIDIA lost earlier byte stores
of a sequence of byte read-modify-writes to one dword. Lane-private
read-modify-writes no longer use atomics.

Tests: a new execution test covers the private aperture reached through a
table load, a literal and a computed address (store, atomic, and both ways
through scratch_*), a callee reached through s_swappc_b64, isolation of 64
workgroups over one or two slots, divergent wave exits with a second dispatch
reusing the slots, and the module shape (no Function array, no binding in a
program without scratch). The guarded memory load fixture skips the slot
acquisition.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-11-02 04:35:35 +01:00
Ondra97 4c4b442a12 fix(shader): retain descriptor phi guards on current main 2026-11-01 17:08:29 +01:00
JJenkx 218ca18e42 fix(agc): render mesh layers within device limits 2026-11-01 06:07:38 -05:00
Dean 5d3ad2112f Merge pull request #10720 from meh7an/perf/shader-fast-f32
perf(shader): let APS5_FAST_F32 compile f32 arithmetic with host float rules
2026-11-01 16:41:29 +13:00
Dean Galvin 7ec2940c11 Merge main into perf/shader-fast-f32 2026-11-01 13:38:19 +13:00
Celegans12 068f2b3ecf fix(shader): reuse bound specialization fields for null buffer slots
Null buffer descriptors still split modules on unused specialization
fields after buffer presence moved to run time. Learn the first valid
bound fields per slot and use them for absent descriptors, retaining
actual runtime presence and independent bound formats.
Snapshot the learned fields once for result memo keys and materialization
so identical null captures cannot retain a module made before learning.
Cover direct, captured and prepared calls, null stores, and changed formats.
Keep the process-local table and an off switch for main's module selection.

AI-assisted: yes
2026-10-31 23:22:39 +01:00
Yunus Shaikh a803318e65 Merge main into feat/shader-sampler-limits
The conflict in core/libs/prx/libSceAgcDriver/CMakeLists.txt from #12862's split is resolved with tools/agc_test_split.py resolve, which moves this PR's test registrations into tests/cmake/.
2026-10-31 15:06:12 -07:00
OpenAI Codex 1dee304edc fix(shader): align image resource size assertion 2026-10-30 21:18:08 -04:00
B-Howell 16f3ce83d6 Merge frozen main into PR #12246 private candidate 2026-10-30 20:14:26 -04:00
Adrià d998343ced Merge pull request #12039 from milescoviello/perf/ir-use-arena
perf(shader): allocate a program's use lists from an arena
2026-10-30 14:38:29 +01:00
B-Howell ba535b163f fix(shader): update Linux image resource layout assertion 2026-10-30 07:57:48 -04:00
Daniele Giovane b215a39ec1 chore(shader): integrate current main before snapshot retry fix 2026-10-30 12:33:23 +01:00
Ondra97 bb83b43b7d chore(shader): reconcile guarded descriptor cache with main 2026-10-30 11:54:36 +01:00
Yunus Shaikh e7b14b0e8e Merge main into feat/shader-sampler-limits 2026-10-30 10:10:09 +00:00
Adrià 25ff0a6d88 Merge pull request #12561 from milescoviello/fix/msaa-sample-adjusted
fix(shader): read a 2D MSAA T# through image_sample_a as its sample 0
2026-10-30 10:56:12 +01:00
milescoviello 0fe2329ee8 Merge main 422f96b3a9 into perf/ir-use-arena 2026-10-30 04:34:36 +00:00
Adrià d0cf19b2cb Merge pull request #12233 from beardsciences/fix/nvidia-mesh-window-buffer
fix(shader): keep mesh register windows out of local memory on NVIDIA
2026-10-30 02:31:36 +01:00
milescovielloandClaude Opus 5.5 f27177dd9b fix(shader): keep image_sample_a out of the cube-face and volume-array image modes
ResourceTracker masks the adjust bit before deciding cubeFaceSample, so the 2D
MSAA plane read takes image_sample_a. That predicate also feeds the cube-face and
2D-array-through-3D modes, which nothing has measured with _a. An image now
records adjustedSample when any of its samples sets the bit, and those two modes
refuse it. Disk cache format 50 for the new ImageResource field.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-10-29 22:49:34 +00:00
B-Howell 0931c89fe9 chore: merge current main for array row sampling 2026-10-29 18:24:00 -04:00
AdriàandClaude Sonnet 5.5 6a98793e3b fix(shader): IrValue is 144 bytes with the use allocator
Co-Authored-By: Claude Sonnet 5.5 <[email protected]>
2026-10-29 21:17:50 +01:00
Christian 6f79055a00 fix(shader): keep mesh register windows out of local memory on NVIDIA
On NVIDIA's proprietary driver, function arrays that live in local memory
and are read under a data-dependent branch return wrong values in
subgroups 1-3 of a mesh workgroup; subgroup 0 is correct. A wave64
geometry program whose relative addressing keeps its VGPRs in the vector
window therefore loses register writes in every wave but the first. In
the clipping geometry program of Sony's PS5 PSP emulator (PPSA07550) the
empty waves never cleared their candidate primitive slots and wrote
degenerate triangles over wave 0's, so the 3D menu drew spikes.

On that driver a mesh program's window now lives in a device-local
storage buffer of 256 workgroup slots of 65536 dwords, claimed through a
per-slot lock and released after the final barrier. The pool is created
before the first draw that uses it records anything, and its header is
zeroed in a batch of its own that is submitted and waited for; the pool
is published only after that wait, and a failure releases it. Direct
register accesses keep one function variable per register; a direct
store also writes the buffer when a buffer read can see it, relative
reads load the buffer, relative writes store only to it, and a direct
read that may follow a relative write loads the buffer and refreshes the
variable. A buffer entry is zeroed only when a buffer read can see it
before a write. APS5_NO_MESH_WINDOW_BUFFER=1 keeps the arrays.
2026-10-29 08:56:39 -04:00
Adrià c33bb03591 Merge pull request #11820 from milescoviello/perf/ir-inline-operands
perf(shader): keep up to three IR operands inside the value
2026-10-29 12:58:07 +01:00
Daniele Giovane 0dbf5478b2 fix(shader): advance nested-table disk format after main refresh 2026-10-29 11:03:24 +01:00
JJenkxandClaude Opus 5.5 e2f86a2047 fix(shader): read shader cache file times natively on Windows
The MinGW std::filesystem::last_write_time reads and sets file times
through the UCRT stat and utime calls, which convert through local time
using TZ. With a TZ other than the Windows zone, including the one libc
applies from the guest environment, times shifted by the difference:
under TZ=IST-5:30 on an Eastern host a temporary written that second
was 9.5 hours old, so housekeeping deleted it, and a TZ west of the host
set the active cache stamp hours in the past. Housekeeping now reads
times with GetFileAttributesExW, refreshes the stamp with SetFileTime
and compares in system_clock. The housekeeping test runs its child
with a TZ 12 hours from the host zone.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-10-28 21:05:40 -04:00
B-Howell 5f2d056129 chore: merge current main into layer-row sampling 2026-10-28 08:59:00 -04:00
Yunus Shaikh 7f4e97c45f Merge main into feat/shader-sampler-limits
# Conflicts:
#	core/shader/recompiler/ShaderDiskCache.hpp
2026-10-28 02:26:39 -07:00
Yunus Shaikh 23194a4002 Merge main into feat/shader-sampler-limits
# Conflicts:
#	core/shader/recompiler/ShaderDiskCache.hpp
2026-10-27 22:09:52 -07:00
B-HowellandClaude Opus 5.5 ca0bc660ce feat(agc): sample 1D arrays past maxImageArrayLayers as rows of a 2D image
A sampled 1D array view with at least maxImageArrayLayers slices, read
only by image_sample_lz or image_sample_l, gets a runtime image mode that
binds a 2D image holding each viewed slice in two adjacent rows. The
shader rounds and clamps the layer as Vulkan array layer selection does
and samples on the boundary between the two copies, so filtering never
reaches another slice. Other uses keep throwing.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-10-28 00:46:02 -04:00
milescovielloandClaude Opus 5.5 02260c6060 perf(shader): keep up to three IR operands inside the value
Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-10-27 11:43:27 +00:00
Daniele Giovane 153400ba2b fix(shader): separate nested-table cache format from main 2026-10-27 10:15:44 +01:00
Ondra97 fefe7bc97e fix(shader): update guarded descriptor source size assertion 2026-10-27 09:12:24 +01:00
Ondra97 7e01f3435e fix(shader): guard rematerialized descriptor reads by source blocks 2026-10-27 09:12:24 +01:00
hugodearaujo b9f4f65904 fix(shader): encode both new image fields under disk cache format 49
main took format 48 and a 45th ImageResource field (optionalDescriptor) with #8077; the merge kept both sides's 48 and 44.
2026-10-27 03:46:24 -03:00
hugodearaujo 5a5e54a455 Merge main into fix/agc-short-cube-sampling 2026-10-27 03:46:24 -03:00
Dean 37c6b4bc25 Merge pull request #8077 from 0xcrstn/ufc6/descriptor-web-fold
fix(shader): split descriptor webs whose paths fold or hold invalid arms
2026-10-27 14:56:47 +13:00
hugodearaujo 787b6a6720 fix(agc): sample cube descriptors with fewer than six slices as six faces 2026-10-26 15:11:35 -03:00
Yunus Shaikh fe85d6c4e3 Merge main into feat/shader-sampler-limits 2026-10-26 07:34:17 -07:00
0xcrstnandClaude Opus 5.5 ec06ba2973 fix(agc): read back descriptor faults of shaders that also use image tables
A shader with an image table map read its fault buffer back only when a
table record was poisoned, an SRT read was poisoned, it had window lane
guards or the loop guard was on. A DescriptorFault only set the fault
buffer, so with a valid table and no copied write nothing ran the fault
check, and a lane that took a folded descriptor web path or selected an
undefined arm read arm 0 or zeros with no report.

The compiled artifact now counts its DescriptorFault instructions
(descriptorFaults, stored in the shader disk cache, format 48), and the
readback gate requests the fault check when it is nonzero. The result a
capture materializes copies the count, and also windowLaneGuards, which
that copy had dropped, so the gate's window lane guard condition never
saw it. sizeof(CompiledShaderArtifact) is 288 and sizeof(RecompileResult)
552 with the new field.

agc_driver_descriptor_web_faults adds a wave32 shader that reads an image
table and then the descriptor web, storing only to LDS so no copied write
forces completion: it binds an image table and no BDA address table, a
valid arm and an unselected undefined arm stay clean, the folded path and
a selected undefined arm fault at the read, and nothing faults with EXEC
empty. Without the gate change the folded case does not fault.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-10-26 14:46:11 +02:00
0xcrstnandClaude Opus 5.5 ac0c125999 Merge upstream main into ufc6/descriptor-web-fold
Resolve the overlap with main's WindowLaneGuard and image-resource changes
by keeping both sides: DescriptorFault sits next to WindowLaneGuard in the
opcode list, metadata and side-effect switch, and its emitter next to
EmitWindowLaneGuard; optionalDescriptor is serialized after
remappedDepth1D; undefinedImageWords follows the new image helpers; the
descriptor web debt entry follows main's new entries.

The ImageResource field-count assertion is derived from the merged
structure (44 fields: main's 43 plus optionalDescriptor). sizeof
(ImageResource) stays 96 and sizeof(MemoryInfo) stays 80, so those
assertions are unchanged. The undefined-format test keeps its captured
regions in a variable, as MemoryRegionView no longer binds a temporary.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-10-26 14:10:30 +02:00