3 Commits

Include renames

Author	SHA1	Message	Date
oskarlgsandClaude Opus 5.5	206aaa56cb	fix(relinker): decode near branches with an operand-size prefix as AMD does ... 66 E8, 66 E9 and 66 0F 80-8F without REX.W take a 16-bit displacement on AMD processors, the console included. Every near relative branch with that prefix truncates its target to 16 bits, so the decoder reports no branch target for it and stubs refuse to move it. Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]> Claude-Session: https://claude.ai/code/session_016TFMtUC4L4wMS4eeEqaNSR	2026-10-17 20:58:29 +00:00
Claude	feb19a844d	fix(relinker): decode 3DNow! instructions with their ModRM and opcode suffix ... 0F 0F was decoded as a two-byte instruction. 3DNow! instructions are 0F 0F ModRM [SIB] [displacement] imm8, the trailing byte selecting the operation (AMD64 Architecture Programmer's Manual Volume 3, Appendix A, 3DNow! opcodes). Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01VZWLdTjf1S57iLgn2rcaFb	2026-10-11 22:21:32 +00:00
Arvind FrøilandandClaude Opus 5.5	0858f01429	test(relinker): check decoder lengths against an LLVM-generated table ... Co-Authored-By: Claude Opus 5.5 <[email protected]>	2026-10-08 21:09:18 +09:00