OpConstantTrue and OpConstantFalse carry no operand word, so they reached the
declaration cache through the variadic Constant template, which builds the key
vector, and paid an allocation on every call. ConstantBool emits both, so a
shader paid it twice per boolean constant. Add the two-word overload; the
compile-shaped benchmark drops from 10413 allocations to 415.
Add agc_spirv_module_tests covering the interning contract: a repeated
declaration returns one id and is emitted once, operand shapes that share a
leading key word stay distinct, integral and enum operands agree, decorated
types stay separate from plain ones, memoized ids survive AllocateId, modules
do not share ids, and ids stay unique and contiguous past the cache capacity.
The test passes against both the previous header and this one, so it pins the
contract rather than the implementation.
Benchmark, pre-optimization header against this one, best of five:
hot loop x 2M 613.6 ms -> 46.3 ms 13.2x
compile-shaped 5000 instr 4.2 ms -> 0.4 ms 10.8x
64 compile-shaped modules 286.0 ms -> 25.4 ms 11.3x
Allocations for the compile-shaped case fall from 55217 to 415. Both builds
compute the same value over the same call sequence.
Co-Authored-By: Claude <[email protected]>
Every SpirvModule::Type and Constant call built a heap std::vector key and
looked it up in a std::map keyed on std::vector, so the comparison walked the
key bytes. At the one to three such calls per emitted instruction a shader
issues thousands of them per compile.
Add a fixed-size, linearly probed declaration cache that holds the key inline
and is consulted before the key vector is built, making a repeated declaration
a hash and a compare. The cacheable shapes are those whose operands are a
word: OpTypeVoid, OpTypeBool, OpTypeInt, OpTypeFloat, OpTypeVector,
OpTypePointer, OpTypeStruct, OpTypeArray, OpTypeFunction and the scalar
OpConstant family. The overloads are constrained on word-sized operands so
that enum operands such as spv::StorageClassFunction reach the cache instead of
binding the variadic template by reference.
Measured with a harness driving the module through the emitters' call shapes:
80000 hot type and constant calls drop from 80074 heap allocations to 140. The
assigned ids and the emitted SPIR-V word stream are byte-identical.
Co-Authored-By: Claude <[email protected]>
The PS5 libthr (FreeBSD) creates error-checking mutexes by default and has
PTHREAD_MUTEX_ADAPTIVE_NP (type 4); relocking an error-checking or adaptive
mutex returns EDEADLK. Default mutexes were Normal and type 4 was mapped to
Normal, so a relock threw instead of returning EDEADLK, which aborted an
Unreal Engine title's recursive directory scan.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The unsupported-instruction error now lists the instruction bytes, and the relink failure names the input file, the main executable or the guest module, on an extra Input: line.
op_sel[1:0] on v_alignbit_b32/v_alignbyte_b32 selects the byte of src2 that
holds the shift, op_sel[2] is ignored and op_sel[3] writes the low 16 result
bits to the high half with the low half zeroed (measured on gfx1035).
v_alignbyte_b32 now uses src2[1:0] only, as the ISA says; values >= 4 gave
a wrong result before. v_max3/min3_{i16,u16} and v_med3_u16 take op_sel like
v_med3_i16 already does.
Co-Authored-By: Claude <[email protected]>
Color targets with the SW_4KB_S swizzle (CB_COLOR_ATTRIB3 tile mode 5) are laid out in 4 KiB
blocks with the standard element order the texture detiler uses, and are resident through the
same storage images as 64 KiB targets. A CB_COLOR_VIEW selecting one slice (SLICE_START equal to
SLICE_MAX) renders into that slice: the target starts one slice size per slice after the surface,
the slice size being the surface's mip chain as a texture of the same tile mode lays it out. Views
of several slices are still rejected.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
v_div_scale_f32 returns a NaN source unchanged instead of scaling it,
and v_div_fmas_f32 quiets the first NaN input or returns the default
NaN 0xffc00000, so results no longer depend on the driver's NaNs. The
test compares NaN results bit for bit. s_denorm_mode throws: the
recompiler does not pin a denormal mode, so no value matches what it
models.
Co-Authored-By: Claude <[email protected]>
These make up the precise f32 division macro compilers emit for a / b. No
reference emulator implements them and the ISA pseudocode disagrees with the
hardware, so the rules were measured on an RDNA2 GPU:
- div_scale decides from the exponent fields only: 2^64 or 2^-64 scaling
and VCC for differences >= 96 or <= -96, a denormal or huge (>= 253)
denominator and a numerator exponent <= 24; a zero input gives 0xffc00000.
- div_fmas scales by 2^64 when the exponent of S2 is >= 128, else 2^-64,
before the single rounding (the ISA says a fixed 2^32).
- div_fixup follows the ISA, and a NaN quotient with finite inputs becomes
+-inf.
s_denorm_mode is accepted and ignored; listed in TechnicalDebt.
Co-Authored-By: Claude <[email protected]>
buffer_atomic_fcmpswap, fcmpswap_x2, fmin_x2, fmax_x2, inc_x2 and
dec_x2 are compare-and-swap loops on the dword or qword. fcmpswap
compares as floats (-0 equals +0, NaN equals nothing) and fmin/fmax are
IEEE minNum/maxNum with -0 < +0, a quieted result for a signalling NaN
and the other operand for a quiet one, all with integer ops so the
driver's float controls do not matter. The existing 32-bit fmin/fmax
kept the old value whenever a NaN or two zeros were involved; it now
uses the same rule.
Co-Authored-By: Claude <[email protected]>
buffer_atomic_inc, buffer_atomic_dec, buffer_atomic_cmpswap_x2 and
buffer_atomic_{add,sub,smin,umin,smax,umax,and,xor}_x2 threw in the decoder.
The 64-bit ones use native 64-bit SPIR-V atomics like the existing
swap_x2/or_x2; inc and dec wrap at the data operand through the existing
compare-exchange helpers.
Co-Authored-By: Claude <[email protected]>
v_mov_b32 accepted SDWA destination selectors for the words only; a byte
destination (dst_sel BYTE_0..3) threw 'VOP1 SDWA destination selector is not
supported'. The write itself already handles bytes and every dst_unused mode
(TranslationContext::writeRawU32). GTA V aborted during boot on such a move
(dst_sel BYTE_0, dst_unused UNUSED_PRESERVE) in one of its eboot compute
shaders. The error now names the selector, opcode and pc. The SDWA destination
execution test covers BYTE_0 and BYTE_2 with UNUSED_PRESERVE and BYTE_1 with
UNUSED_PAD.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
addrlib sizes a non-tail level with ShiftCeil; the layout used the image's
rounded-down extent, so volumes with a non-power-of-two width or height (33x20x12
in the new test) got a different layout.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
3D textures with more than one mip level were refused. Each slab of
blockDepth slices of a thick (SW_4KB_S / SW_64KB_S) volume now holds the
whole mip chain, smallest level first and level 0 last, as 2D chains are
laid out. A level's depth halves per level, so the texture loops skip the
slices a level does not have. Thin 3D (D/R 64KB_X) chains use the 2D mip
layout per depth slice. Thick mip tails still throw.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
Decode VOP3b 0x177 and translate it next to v_mad_u64_u32: the high half of
the product comes from SMulHi, and the carry-out is the sign of the exact
sum (bit 64 of the sign-extended product plus the sign-extended addend), as
measured on RDNA2 hardware.
Co-Authored-By: Claude <[email protected]>
Loads at fs:1 through fs:0x27 read tcb_dtv and tcb_thread on the FreeBSD layout, which the Windows thread control block does not model, so they returned zero. Accept only the TLS block, fs:0 and the stack guard at fs:0x28, and fail the relink for the rest.
Pouare514