StorageTextureBudget reserved the larger of the sampled textures alive
and their 2 GiB floor. The sampled budget already reserves
TextureCacheBudget, at least the storage cap, for the storage cache, so
on an 8 GB card the two caches each kept the other's maximum: with
3936 MiB used outside the caches on a 7189 MiB budget and 49 MiB of
sampled textures, the storage budget came out at 306 MiB and sat at its
512 MiB floor while about 2.7 GB of the budget stayed free.
The storage budget now reserves the sampled textures alive and gives
room back as they grow, at its next read. Where they hold 2 GiB or more
the budget is unchanged.
On RDNA 2, an S# with TRUNC_COORD 0 rounds the scaled coordinate to 8
fractional bits, ties to even, and one with TRUNC_COORD 1 truncates it,
for point and bilinear filters. The S# decoder ignores the bit, and
AMD's Windows driver truncates for nearest samplers and rounds for
linear ones, so a TRUNC_COORD 0 point sample just below a texel edge
reads the texel below it. The code comment said the bit moves texel
selection by half a texel at most; the debt entry records the measured
rule instead.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The blocked-destination case checks a different file, so an in-place
rewrite passed it. The earlier case is back beside it: a directory at
<name>.tmp makes the write fail, and the previous aps5-bench.json.gz must
be unchanged. It is left out of Windows builds, where the
std::ios_base::failure thrown inside the MinGW ofstream did not unwind to
the test's catch.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
A recorded comp-to-single clear stayed valid for its surface address,
size and sample count until another recognized clear replaced it, so a
surface freed and reallocated on the same memory could import the old
color for its 0x10 DCC keys. The record now also carries the image's
pipe-bank XOR, which RADV assigns per image, and is dropped when an
unmap or allocation removal covers the surface's base.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
RADV's comp-to-single shader stores user data 5 to 8 as the four dwords of
sample 0's texel: v0 from s5, v1 and v2 from s[6:7] through a 64-bit shift by
zero, and v3 from s8. RADV binds the image through a uint view of the texel's
size, up to R32G32B32A32_UINT, so a 64-bit texel takes the first two dwords
and a 128-bit texel all four. 0x10 keys of RGBA16F and RGBA32F targets now
import as a clear to the recorded color instead of being refused.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
RADV clears a multisampled DCC target to a color other than 0000, 0001,
1110 or 1111 with radv_clear_dcc_comp_to_single: a compute dispatch stores
the color at the first pixel of every DCC block through a uint storage view,
and the DCC keys become 0x10. The driver refused that view of a resident
target, made a separate target in the view's format otherwise, and couldn't
import 0x10 keys.
The dispatch is now recognized by its code and not run. Its clear color is
recorded for the surface its image descriptor names, and 0x10 keys on a
multisampled target of that surface, size and sample count import as a clear
to that color, for texels up to 32 bits.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Without VK_EXT_shader_stencil_export (NVIDIA), stencil reference exports
are emulated by replaying the draw once per value. An export the prover
could not bound to at most 16 values was refused. The replay shader
compares the export's low eight bits, so an unbounded export now
replays all 256 values, and proven values are reduced to their low
eight bits as the comparison sees them.
Refs #4276
Co-Authored-By: Claude Opus 5.5 <[email protected]>
DecodeState and DrawRejection rejected PA_CL_CLIP_CNTL bit 16
(CLIP_DISABLE), skipping draws that set it. Vulkan handles viewport
guard-band clipping automatically without requiring explicit clip
toggles. Accept bit 16 in ClipControlMask without altering depthClamp,
and record the unmodelled console clipping behavior in technical debt.
Tested with agc_driver_graphics_tests.
Adrià