ds_add_f32 and ds_add_rtn_f32 now follow the measured hardware: both
operands are flushed to a signed zero when bit 0 of the f32 denormal field
is clear and the result when bit 1 is clear, the sum is rounded to nearest
even, a NaN data operand is stored quieted, else a NaN old value is stored
quieted, and +inf + -inf stores 0xffc00000. Measured on gfx1010 and, in
#5492, on gfx1031.
The new MemoryInfo field is stored in the shader disk cache (field count
31, minimum record 79 bytes, FormatVersion 34). The parts that depend only
on the data operand are computed once, before the CAS loop.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
The Windows error for a refused FindFirstChangeNotification was one string shared
by WatchParent and WatchContents, so the log could not tell which handle or path
was denied. Build it from the watcher, the path the API was given and
GetLastError instead.
Still throws: the EVFILT_VNODE attach path is vfs_kqfilter, which returns only
EINVAL, ENOMEM or 0, with EBADF from fget before it, and consults no directory
permission, so no FreeBSD errno stands for a host that refuses to notify.
The README no longer embeds history.svg; it links history.html, which the progress page also links.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Main's flatVolumeLineCompatible change also took format 34 with another layout, so entries of either would load as the other.
Co-Authored-By: Claude <[email protected]>
Move bounded vertex folding and empty-image feedback into separate topics. Keep the replay coverage proof, stage contracts, finite-reference tests and mapped cache regressions; version the stencil layout separately as format 34.
Co-Authored-By: Codex <[email protected]>
Preserve instance and triangle order with one dynamic-reference shader pipeline. Require bounded references, complete export coverage, replay-safe mask control and resources; refuse unsupported side effects and feedback.
Co-Authored-By: Codex <[email protected]>
A draw with PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES > 0 and
PA_SC_MODE_CNTL_0.MSAA_ENABLE clear threw. On GFX10 and later the bit
is what makes the rasterizer use the programmed sample locations; with
it clear the draw now keeps the target's sample count with every sample
at the pixel center. Points, lines, a depth target and
alpha-to-coverage still throw.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
GPU and DRIVER need APS5_PROFILE_GPU or APS5_PROFILE_DRAW, and those switches add timestamp queries to every batch and timers to every packet, which changes the timings the panel shows. A screenshot of such a run could pass for an unprofiled one, so while either switch is on the panel now starts with a PROFILED line.
SHADERS counted the pipelines created between the first and the last present of the last second, so below 1 fps, with one present in that second, it read 0, as FPS did before. It now counts those created during the last frame there, like the other lines. The statistics test checks DRAWS, DISPATCH and SHADERS for a present alone in its second.
USAGE.md explains DRAWS, SHADERS, VRAM, RAM and RES, where each number
comes from, the count and memory formats, and what counting costs while
the overlay is hidden.
The front-face VGPR was always +1.0 / -1.0, which is its form only while
FRONT_FACE_ALL_BITS is clear (current Mesa reads it with fgt 0 / fsign).
With the bit set, as Mesa 22.0 RADV programs it, a back face reads 0 and
a front face non-zero: ACO then tests it with v_cmp_lg_u32 0. Uncharted:
Legacy of Thieves Collection (PPSA05684) sets the bit and its two-sided
cloth shaders test v_cmp_lt_u32 0, so -1.0 (0xbf800000) made every back
face a front face: the insides of the menu skeleton's rags kept their
front normals and were lit white by the spot light behind them.
The pixel stage info now carries the bit (request version 26, cache and
draw keys), the decode reads SPI_BARYC_CNTL when FRONT_FACE is an active
input, and the translator turns the builtin into 0xffffffff / 0. The
exact front value is not measured (docs/dev/debt/shader.md).
AI-assisted: yes
On ds_ordered_count M0 holds the ordered wave ID, not a GDS address as
for ds_append: radeonsi and ACO pass the wave ID as the intrinsic's
pointer and keep the counter address in offset0. Reading M0 as the base
and size skipped the add whenever M0[15:0] was 0, so every wave got the
same range. The test now runs the ordered pass with M0 = 0 and M0 = 7.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
ds_ordered_count adds the first active lane's value to a GDS counter and
returns the previous value, like ds_append adds the lane count. Waves are
not serialized in launch order: each still gets its own range. Ordered
swap and multi-dword counts stay refused. DISPATCH_DIRECT and
DISPATCH_INDIRECT accept ORDERED_APPEND_ENBL (bit 3) of the initiator.
Compute shaders of MXGP 26 (PPSA30839) use both.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
A plan copied every control-flow condition with all its operands, though one
that depends on a vector register is never evaluated. Such conditions are
dropped, and the copied values live in one arena without use lists.
VGT_TF_PARAM.PARTITIONING 3 now compiles to Vulkan's fractional-even
spacing, which radeonsi programs as PART_FRAC_EVEN. Its factors are
bounded at 64 like integer partitioning; Vulkan raises the remaining
ones to at least 2, the D3D11 range for this mode.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Leonardo