A sampled 32_UINT or 32_SINT T# with a depth swizzle that no live depth
surface matches threw, while the 16-bit case already falls back to guest
memory through an R16_UNORM view. The 32-bit case now reads the guest
bytes through an R32_SFLOAT view, which the shader casts back to the
stored dword.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The test now sets a base bound of 32 entries and a first shrink window
of 2 (ResourceCache::SetBase, applied at the next Clear()) and turns
dispatch recipes off, so every dispatch goes through the cache: grow,
shrink, regrow, backoff and the Clear() reset take about 1.2k
dispatches instead of about 100k.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01XBXM4pgkMHYEtqN1EQni2P
A row scan (DPP row_shr 1, 2, 4 and 8 over keys that hold the identity on
lanes the wave did not enter with) read with v_readlane at lane 15, 31, 47
or 63 shuffles from lanes that already left the surrounding loop, which are
inactive on the host and whose values are undefined there. The read becomes
a subgroup reduction over the active invocations of that row, per wave32
half when a wave64 host subgroup holds two waves. The saved exec mask set to
every lane (`!x || x`) also counts as every lane.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Seven test fixtures create their own command pool without
VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT, while the driver's own
pool sets it and Recorder begins a used command buffer again without an
explicit reset. The Khronos validation layer reports
VUID-vkBeginCommandBuffer-commandBuffer-00050 in depth_storage and
partially_resident_snapshot --pending-stores for this. The fixtures now
create the pool the way VulkanDevice does.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
#6243's new head merges main f1af6c5915, whose #7325 adds
verifyChainedTableOffset next to the selected-record tests this
branch carries from #6243. That test reads the record words from the
snapshot's shared word list; this branch keeps the words with each
table's snapshot, so the merge reads them from the table it checks.
PerformanceTrace kept the recording flag and each thread's trace buffer
as inline static members, so on Windows every module that includes the
header had its own copies: agc_driver_registration_trace read an empty
pointer, and libSceVideoOut's timers never saw the trace recording. They
are now defined once in the driver.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The recompiled vertex shader writes gl_ClipDistance through a variable of
its own beside its position block, but the rect-list control and
evaluation stages read and wrote it as a second member of their
per-vertex block, so the stage interfaces did not match
(VUID-RuntimeSpirv-OpVariable-08746). They now take and forward the clip
distances through ClipDistance variables of their own.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
set_tests_properties replaced the ASAN_OPTIONS that add_asan_test_options appends to
guest_module_args, guest_deferred_dependencies and guest_module_fini in ASan builds.
Append the TMPDIR, TEMP and TMP settings instead.
Main's #7325 adds verifyChainedTableOffset to the image table tests
where this branch adds its selected-record tests. Keep both, with
main's call after this branch's.
Main's EmitSetAttribute debt entry now says the generated rect-list and
barycentric tessellation stages forward the vertex shader's clip array.
It sits next to this branch's PERSP_SAMPLE and pixel position entries,
which main left as they were; keep main's entry and this branch's two.
sceVideoOutSubmitFlip went through queue 0 as a one-packet command
buffer, so every CPU flip waited until the queue worker had translated
all command buffers submitted before it. The PS5 RADV WSI flips from its
own thread once the frame's fence has signaled. vkQuake keeps two frames
in flight, so by then the next frame's command buffer is already queued,
and the flip waited about 10 ms for the worker to translate it. Presents
came in pairs, about 4.7 ms and 29 ms apart. Meanwhile the title waited
in acquire for the flip to be shown, leaving the worker idle for about
7.5 ms per pair.
A CPU flip from a thread that has never submitted queue-0 work now goes
to the presenter at once, unless a command-buffer or EOP flip ahead of it
has not been reached yet. Such a thread can only know that its frame is
done by waiting for it. A flip from a thread that submits its own frames
still waits for the work submitted ahead of it, because a title that
flips without waiting for its frame relies on that order.
APS5_CPU_FLIP_IN_ORDER=1 orders every CPU flip.
vkQuake (PPSA99010) on an RTX 4060: 60 -> 72-74 presents per second,
present-interval standard deviation 12.2 -> 2.1 ms, and intervals over
25 ms 40% -> 1%.
Romans Pokrovskis