Resolve the overlap with main's WindowLaneGuard and image-resource changes
by keeping both sides: DescriptorFault sits next to WindowLaneGuard in the
opcode list, metadata and side-effect switch, and its emitter next to
EmitWindowLaneGuard; optionalDescriptor is serialized after
remappedDepth1D; undefinedImageWords follows the new image helpers; the
descriptor web debt entry follows main's new entries.
The ImageResource field-count assertion is derived from the merged
structure (44 fields: main's 43 plus optionalDescriptor). sizeof
(ImageResource) stays 96 and sizeof(MemoryInfo) stays 80, so those
assertions are unchanged. The undefined-format test keeps its captured
regions in a variable, as MemoryRegionView no longer binds a temporary.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
A branch into a skipped word was only reported when the sweep ended at
s_endpgm or s_code_end; a sweep that ran to the end of the code threw
the generic code-boundary error instead. Only the decoder's error types
are skipped now, so other exceptions propagate, and the debt entry
records the exception per skipped word and what a misaligned sweep
through an unreachable span puts in the program.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The RDNA program decode sweeps linearly up to the last s_endpgm past the
furthest direct branch target, so it also decoded words that no path
reaches and threw on any it could not decode. A word directly after
s_branch, s_endpgm or s_code_end that fails to decode is now skipped;
the decode still throws that word's error when a direct branch or
s_call_b64 targets it, and a failure on a word reachable by fall-through
is unchanged. The control-flow graph starts the block after s_branch and
s_endpgm at the next decoded instruction instead of the next word.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Since the synthetic FMASK mode was removed, a direct FMASK load reads
the stored word and only Fmask32_S8_F8 is accepted. A load from any
other FMASK format of up to 8 samples now reads the 8-, 16- or 32-bit
surface and expands it in the shader to 4 bits per sample, an index
past the fragment count reading 8 (unknown). One runtime image mode
handles every such format, reading the format from the descriptor at
run time or from a specialization constant.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The SOPK branch of the GCN decoder never set the literal for
s_setreg_imm32_b32, so the eight-byte instruction was re-encoded as one
word and its decode threw "literal operand word is out of the code span
bounds". The decoder now copies the literal for that opcode; the new
agc_gcn_decode test decodes the reported stream.
Co-authored-by: javierUDP <[email protected]>
Co-authored-by: Savvanis Spyros <[email protected]>
Each GCN instruction is re-encoded to its RDNA form and decoded by the
existing RDNA decoder, so the PS4 path shares the recompiler. Covers the
legacy VS stage (program at the VS slot, user SGPRs from s0, vertex and
instance index in v0-v3), fetch shaders linked as user-data calls, MIMG
(image_sample and friends), PS4 buffer descriptors (GCN DATA_FORMAT /
NUM_FORMAT, 44-bit base) and T# image descriptors (GCN tiling in word 7).
The GCN switch is keyed into the shader disk cache. PS5 behaviour is
unchanged: every PS4-only rule is gated on GcnGuestShaders().
Death Stranding 2 (PPSA02015) registers shaders with both and stops on
0xc8 ("unsupported MIMG opcode 0xc8"). LLVM's gfx1030 disassembler reads
the same words with bit 0 clear as image_gather4_c and image_gather4_c_o,
and the _a rows already in the table are the base opcode plus 0x80 with the
adjust flag, so both reuse the existing compare gathers with the adjust
flag set.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01BywPXoZACVi8ALV4JKvuPZ
The decoder refused v_dot2_f32_f16 whenever op_sel[2] or neg_hi[2] was set
or op_sel_hi[2] was clear. On an RX 6700 XT the f32 accumulator ignores
op_sel[2] and op_sel_hi[2], neg_lo[2] negates it and neg_hi[2] takes its
absolute value (both together give -|c|), as for v_fma_mix. The decoder
now normalizes the accumulator's selects and turns neg_hi[2] into abs.
Float16Dot's refusal checks become run checks of the five accumulator
variants against values measured on the same rows.
Co-Authored-By: Claude <[email protected]>
A path of a descriptor web whose dwords depend on the program counter, EXEC
or a lane mask selected the first descriptor, and an image arm whose words
are not a T# was bound as a null image. Both are assumed never to be taken,
but nothing reported it if a lane took one, so a wrong image or zeros went
unnoticed.
The folded path now gets its own selector value, which still selects the
first descriptor and records an InvalidDescriptor BDA fault (new IR
DescriptorFault) when a lane reaches the read with it. An image arm is
checked in the shader with the words the selected arm read: not a null
descriptor, and a TYPE from 2 to 7 or a FORMAT outside the GFX10 image
format table records the same fault with the arm's first two words. Both
faults are recorded only for lanes the image instruction's EXEC enables. The
materializer binds a null image only for exactly those words; any other
invalid arm is refused as before. The GFX10 format ranges are shared
between both checks. A web whose every path is folded no longer leaves its
selector Phis in the program.
Only reads split through a descriptor web bind the fault buffer, which
keeps their dispatches out of pipelined dispatch and stencil replay; splits
along incoming edges keep requiring a valid T# and bind none. The debt entry and
the APS5_STRICT_DESCRIPTOR_WEBS row say so, and note that a shader that
also uses an image table reads its fault buffer back only when a table
record is poisoned.
The descriptor Phi and undefined format tests expect the fault buffer only
for descriptor webs, and a T# shared by every arm of a split S# must stay
mandatory. agc_driver_descriptor_web_faults dispatches a web with two SRT
arms, each over its own texture, and a program-counter path: a lane on
either valid arm reads that arm's texture without a fault, a lane on the
folded path or on an undefined arm faults at the read, and nothing faults
or is written with EXEC empty.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
validImageDescriptor accepted any nonzero FORMAT, so words that are no T#
passed whenever their TYPE nibble was 8 or more. An optional descriptor web
arm holding such words was then not bound as a null image, and the dispatch
failed on a sampled image of an unsupported format instead. PPSA23566
(UFC 6) has such an arm (formats 402-463): a compute shader picks one of 32
SRT T#s through an s_setpc_b64 jump table indexed by min(i, 32), and the
default entry reaches the image_sample_lz with the loop-entry value of the
T# registers, which a constant-buffer load filled with floats. The console
never samples that arm: the default entry is taken only from iteration 32
on, when the registers hold iteration 31's T#.
A FORMAT outside the GFX10 image format table (Mesa gfx10-rsrc.json
GFX10_FORMAT: 1-77, 128-154, 156-182, 265-292) now makes the descriptor
invalid. An optional descriptor web arm is bound as a null image, as other
invalid arms are; a direct image is refused as invalid unless it is a null
descriptor, and an image table entry faults when selected with the
InvalidFormat reason.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
v_cubeid_f32, v_cubesc_f32, v_cubetc_f32 and v_cubema_f32 refused any
output modifier with "VOP3 source modifiers are not implemented";
PPSA11386 stops there on v_cubeid_f32 v, v, -v, -v div:2.
On RDNA2 (gfx1036), over 2048 inputs in every combination of IEEE mode,
the four f32 denormal values and f16/f64 denormals flushed or kept, with
round to nearest even, the four instructions apply mul:2, mul:4 and
div:2 whenever IEEE mode is off, also with f32 output denormals kept,
where v_mul_f32_e64 in the same kernels ignores them, and ignore them
with IEEE mode on. Where applied, the result is the existing bit-level
f32 output modifier result, and clamp is applied after it.
The decoder accepts the modifier on the four instructions. floatCube
applies the shared f32 scaling, now scaleF32Result, in those modes and
writes with the modifier cleared, so clamp is still applied after it.
With IEEE mode on the signaling NaN quieting applies and the modifier is
ignored; with it off the quieting does nothing and the modifier is
applied. agc_driver_vop3_cube_clamp checks each instruction with each
modifier against tables captured on gfx1036.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01Fnrk5Dazjb2tLooVSpdRQq
Reading src_shared_base, src_shared_limit, src_private_base or
src_private_limit (scalar source codes 235-238) refused the shader since
#1940, because their values were unknown. They now read as the 64-bit
apertures that the flat routing from #1190 classifies: a base is the
aperture's high dword over a low dword of 0, a limit is the same high
dword over 0xffffffff (shared 0x80000000, private 0x70000000).
A 64-bit read (s_mov_b64, a 64-bit VALU source, a wave64 lane mask)
gets the whole value and a 32-bit read gets the low dword. A flat
pointer built from the high dword therefore reaches LDS or scratch, and
64-bit compares against the limits order as on the hardware. The flat
routing and the reads share one definition of the two high dwords.
Sources: LLVM SIRegisterInfo.td (aperture registers are 64-bit, their
low 32 bits are always 0 for a base and -1 for a limit) and
getSegmentAperture in AMDGPULegalizerInfo.cpp and SIISelLowering.cpp
(a 64-bit read whose high half is the aperture); the RDNA 2 ISA guide,
sections 5.2, 5.8 (SH_MEM_BASES holds 16-bit bases) and 9.3; the KFD's
MAKE_LDS_APP_LIMIT (limit = base | 0xffffffff); the gfx1030 and gfx1035
readouts on #1190 and #3803. The PS5's two high dwords stay inferred,
as the shader technical debt records.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Forspoken (PPSA03984) has a pixel shader with
v_interp_p2_f16 v1, ..., v7 op_sel:[0,0,0,1], and main throws
"VOP3 interpolation modifiers are not implemented" one second after
start.
On GFX10, op_sel[3] of a 16-bit VOP3 result selects the high half of
the destination and keeps the other half. The decoder already maps
that bit to destination.sdwaSel 5 for the other 16-bit VOP3 ops, and
write16Bits/writeRawU32 then insert the result into bits 31:16 and
keep bits 15:0. v_interp_p2_f16 is the only 16-bit-result
interpolation instruction, so only it accepts the bit; other op_sel
bits and the bit on the 32-bit-result p1ll/p1lv forms are still
refused.
agc_vop3_interp_decode checks the decoded selector with and without
the bit, and that v_interp_p1ll_f16 still refuses it. In
agc_driver_interpolation_f16 the second v_interp_p2_f16 now writes the
high half of a register holding 0x00001234, and the GPU result must
keep 0x1234 in the low half.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
v_cvt_f32_ubyte0 accepts every SDWA source selector, but the other three byte
conversions had no VOP1 SDWA rule, so any SDWA source select on them was refused
("VOP1 SDWA source selector 4 of opcode 0x12 at pc 0xfcc is not supported").
The selected and optionally sign-extended source goes through the same operand
path as for ubyte0 before byte N is extracted: SDWA supplies source 0 (RDNA 2 ISA
guide 6.8 and 13.3.7) and the opcode reads S0.u[8N+7:8N] (12.8).
agc_driver_sdwa_cvt_f32_ubyte: WORD_0 and WORD_1 selects on ubyte1, and
sign-extended WORD_1 and BYTE_3 selects on ubyte2 and ubyte3.
Guest texture formats 51 (SNorm) and 55 (SInt) of the 10-bit packed group were missing from the texture lookup and the descriptor format table, so a descriptor using them threw 'unsupported guest texture format' while the UNorm (50) and UInt (54) siblings worked. Map them to A2B10G10R10_SNORM_PACK32 / A2B10G10R10_SINT_PACK32, classify them for sampling (float / signed integer), and list SINT among the integer formats.
Co-Authored-By: Claude Sonnet 5.5 <[email protected]>
v_cvt_i16_f16 with mul:2, mul:4, div:2 or clamp in the VOP3 encoding
stops the recompiler with "VOP3 source modifiers are not implemented".
On gfx1036 (Radeon 610M) the result is identical with and without
mul:2, mul:4, div:2 and clamp combined with mul:2, for all 66 measured
inputs; clamp on its own is not a measured case.
The decoder now accepts omod and clamp on v_cvt_i16_f16 and drops them,
as measured. Clamp without an output multiplier is accepted by the same
rule: clamp with mul:2 gives the same hardware result as mul:2 alone.
Matches 528 of 528 rows in two float modes, 0 differing.
v_cvt_u16_f16 is not measured and stays refused.
Co-Authored-By: Claude Haiku 5.5 <[email protected]>
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
v_cvt_pknorm_i16_f16 and v_cvt_pknorm_u16_f16 with |x|, -x or op_sel in
the VOP3 encoding stop the recompiler with "VOP3 source modifiers are
not implemented", although the RDNA2 hardware executes them.
These two opcodes now use the two-source f16 modifier path of
v_pack_b32_f16: op_sel picks the high half of either source, then abs
and neg apply. Other op_sel bits, clamp and omod are still refused.
Matches 15632 of 15632 rows measured on gfx1036 (Radeon 610M) in two
float modes, 0 differing.
Co-Authored-By: Claude Haiku 5.5 <[email protected]>
The decoder throws "VOP3 source modifiers are not implemented" for
VOP3-encoded float compares (v_cmp_*_f16/f32/f64) that set the clamp
bit, so shaders using them fail to compile.
On RDNA2 hardware the clamp bit does not change the result of a float
compare: the measured results with and without it are the same. The
decoder now accepts the bit on float compares; clamp on other carry-out
and scalar-destination opcodes still throws.
Co-Authored-By: Claude Haiku 5.5 <[email protected]>
The assembler encodes the unused third source of the VOP3-encoded
interpolation forms as the inline constant 0 (src2 = 0x80, bit 25 of the
second word), which the decoder refused. Accept that encoding and refuse
any other third source. The decode test now uses the assembler words for
every accepted form and keeps the refusals one field away from a valid
word.
v_interp_p1_f32_e64, v_interp_p2_f32_e64 and v_interp_mov_f32_e64
(VOP3Interp opcodes 0x200, 0x201 and 0x202) reach the decoder as VOP3
and were refused as unimplemented VOP3 opcodes. Decode them into the
existing VInterpP1F32, VInterpP2F32 and VInterpMovF32 opcodes with the
VOP3Interp operand layout, so the interpolation translation already
used by the VINTRP encodings handles them.
Encodings and operand layout follow LLVM's gfx10 MC tests for
VOP3Interp_Real_gfx10 (D69348). The interpolation parameter is the low
six bits of src0, the channel bits 6:7, the coordinate (or the
interpolation parameter of the mov form) is src1, and clamp and omod
reach the destination. op_sel, the packed-half selector, a third source
and abs/neg on operands that do not exist throw.
v_cvt_f16_u16 SDWA only accepted word and dword source selects. Silent
Hill Townfall (PPSA33286) converts the top byte into the low half of a register
and keeps the high half (src0_sel:BYTE_3 dst_sel:WORD_0
dst_unused:UNUSED_PRESERVE), so its shaders failed to recompile. The
generic SDWA source path already zero-extends byte selects, which is the
u16 value the conversion expects, so the rule now accepts every source
select, with whole and partial destinations.
agc_driver_sdwa_cvt_f16_u16 runs four byte selects with dword, WORD_0
and WORD_1 destinations on the GPU and checks the converted halves and
the preserved bits.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
(cherry picked from commit d55dfe8b33)
Dean