validImageDescriptor accepted any nonzero FORMAT, so words that are no T#
passed whenever their TYPE nibble was 8 or more. An optional descriptor web
arm holding such words was then not bound as a null image, and the dispatch
failed on a sampled image of an unsupported format instead. PPSA23566
(UFC 6) has such an arm (formats 402-463): a compute shader picks one of 32
SRT T#s through an s_setpc_b64 jump table indexed by min(i, 32), and the
default entry reaches the image_sample_lz with the loop-entry value of the
T# registers, which a constant-buffer load filled with floats. The console
never samples that arm: the default entry is taken only from iteration 32
on, when the registers hold iteration 31's T#.
A FORMAT outside the GFX10 image format table (Mesa gfx10-rsrc.json
GFX10_FORMAT: 1-77, 128-154, 156-182, 265-292) now makes the descriptor
invalid. An optional descriptor web arm is bound as a null image, as other
invalid arms are; a direct image is refused as invalid unless it is a null
descriptor, and an image table entry faults when selected with the
InvalidFormat reason.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The descriptor web fold covered only program-counter values. PPSA23566
(UFC 6) compute shader 0x1163c84000 also has a path whose T# registers hold a
lane mask accumulated in a loop ("a Phi that does not resolve to one value:
Phi(CompositeExtractU32x4(Ballot(FPUnordGreaterThanEqual32), ...), BitwiseAnd32(...))"),
and throws on it while a career fight loads.
Treat EXEC and Ballot results like the program counter, also through loop
Phis: such a path selects the first descriptor, as before f5ba4e9c6.
Unwritten registers keep their own image. APS5_STRICT_DESCRIPTOR_WEBS=1
throws as before. The descriptor Phi test expects the program-counter, EXEC
and compare-mask entries to plan the loop's two SRT T#s.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
f5ba4e9c6 made a T# split across SRT descriptors throw when one path's
descriptor dwords depend on the program counter. Such a path appears when a
loop's entry edge reaches the read with registers left from s_getpc_b64; a
descriptor built from the program counter is garbage on hardware too, so the
path does not reach the read in a working title. PPSA23566 (UFC 6) throws on
this for compute shader 0x1163c84000 while loading a career fight ("descriptor
web: a descriptor dword depends on the program counter").
Select the first descriptor on such a path again, as before f5ba4e9c6, for
program-counter values only; EXEC and compare-mask values still throw.
APS5_STRICT_DESCRIPTOR_WEBS=1 throws as before. The descriptor Phi test now
expects the program-counter entry to plan the loop's two SRT T#s.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
On PS4 firmware 10.71 sceNetInetPtonEx reads IPv4 text the way
inet_aton does, not the way sceNetInetPton does: "1.2.3" is 1.2.0.3,
"127.1" is 127.0.0.1, hex and octal parts are accepted, a part value
wraps at 32 bits ("1.4294967296" is 1.0.0.0) and the text ends at the
first whitespace. Two differences from BSD inet_aton were measured: a
part starting with "09" is decimal ("0989" is 989), and an octal part
containing 8 or 9 fails.
The flags argument changed nothing for 0, every single bit up to
0x100, 0x10000, 0x80000000 and -1, so it is ignored instead of
throwing. IPv6 still converts as sceNetInetPton does, which matches
the console.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Without VK_EXT_shader_stencil_export (NVIDIA), stencil reference exports
are emulated by replaying the draw once per value. An export the prover
could not bound to at most 16 values was refused. The replay shader
compares the export's low eight bits, so an unbounded export now
replays all 256 values, and proven values are reduced to their low
eight bits as the comparison sees them.
Refs #4276
Co-Authored-By: Claude Opus 5.5 <[email protected]>
DecodeState and DrawRejection rejected PA_CL_CLIP_CNTL bit 16
(CLIP_DISABLE), skipping draws that set it. Vulkan handles viewport
guard-band clipping automatically without requiring explicit clip
toggles. Accept bit 16 in ClipControlMask without altering depthClamp,
and record the unmodelled console clipping behavior in technical debt.
Tested with agc_driver_graphics_tests.
Implement sceNetGetIfName, sceNetGetRandom, sceNetMemoryAllocate and
sceNetMemoryFree with the signatures shadPS4 uses, and cover them in
guest_sce_net_tests.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
Add sceMoveInit, sceMoveTerm, sceMoveOpen, sceMoveGetDeviceInfo and
sceMoveSetVibration, and replace the throwing stubs of the other six
exports. Behaviour and error codes follow shadPS4; signatures follow
Orbital. A guest test covers the init state, argument checks and the
no-controller results.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01Arbzg9c2DA4DEFKVSvRgYv
Port the firmware filter for every text type, with the two codepage sets derived from the firmware converters, and declare sceImeCheckFilterText as unimplemented.
Windows.Gaming.Input stays on by default, so racing wheels, arcade and
flight sticks, HID pads without an HIDAPI driver and Xbox One/Series
trigger rumble keep working. Hosts where it faults at
Windows.Gaming.Input.dll+0x10a84 set APS5_NO_WGI to turn it off.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
