Before two flips have ended a frame nothing was evictable, so a cap retry
was refused and aborted where main served it. Until then imports age by
lookups as before; once frames exist the frame rule applies. A frame end
now moves its own counter, used by the evicting-refusal memory, not the
imports epoch, so the address-space cache survives a flip.
Keep the auth and auto-redirect flags, headers and the auth-info and
pre-send callbacks in Http2::Settings, so requests copy them from their
template and they freeze once transport exists. Accepted kinds, error
codes and their order follow the firmware 13.42 module as reported in
the review: option, header and callback calls reject contexts and
cookie boxes, sceHttp2AuthCacheFlush validates the context,
sceHttp2RedirectCacheFlush ignores its argument and the auto-redirect
flag keeps the stored int.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
Claude-Session: https://claude.ai/code/session_01QdXm6rjuENJGYLZh5hc8cQ
refreshImports checked every live host import, failure and refusal
again at each guest allocation registry change. A title that maps
memory often (SuperTuxKart, ~1650 maps a second) paid a walk that grew
with the live imports: ~34 FPS with ~1.1 GiB of imports on RADV.
The import table now keeps a weak_ptr snapshot of the ranges it was
last checked against and diffs it with the new lease. Only imports
whose import window touches a changed span, and imports made since the
last refresh, are checked again. Every import is checked when the window
is 0 or the window or budget changed. SuperTuxKart's menu goes from
~34 to ~45 FPS with the same imports live.
The entry for the M5 running macOS 26.4 did not say what Rosetta does
with SHA or AVX-512, and the XSAVE entry was measured only on macOS
27.0.1. On that host sha1rnds4 and a 256-bit-wide vpaddd on zmm raise an
illegal instruction alongside RDSEED, CLWB, RDPID, ADCX and ADOX, while
XSAVE writes an XSTATE_BV of 0x7 and XGETBV returns the same x87, SSE
and AVX mask although CPUID leaf 1 still reports neither XSAVE nor
OSXSAVE.
The BMI1 and BMI2 results were compared with the Intel SDM definitions
over 200,000 random inputs each for PDEP, PEXT, BEXTR, BZHI, LZCNT and
TZCNT, so the entry can say they compute the documented result rather
than only that they avoid a fault.
USAGE.md's performance overlay section now gives F10's cycle (off, page
1, page 2, off) and ANYPS5_OVERLAY=2, a table with one row per line of
page 2 that names each source and the system it comes from, and what the
page costs: the trace totals it turns on while it shows, and the checks
and counters that run while the overlay is hidden or on page 1.
ENVIRONMENT.md's ANYPS5_OVERLAY row lists page 2.
A depth plane and the color storage image that holds or receives its texels were copied image to buffer, then buffer to image. With VK_KHR_maintenance8, which the device already enables, vkCmdCopyImage copies the depth aspect directly to and from a single-component color format of its size (D32 with R32, D16 with R16), so those copies record one image copy and two barriers in place of the staging buffer round trip and three barriers. TakeStorage keeps its discard of the new depth surface before the copy. 24-bit depth, the stencil plane and every other format pair keep the buffer path, as does APS5_NO_DIRECT_DEPTH_COPY=1. The graphics Context now carries the maintenance8 flag. No performance claim is made.
Nithishvelan M