The device-dependent skip accepted any wrong result on a device without
f64 DenormPreserve, and a run that excused rows still reported a pass.
Require the result to match a flushed mode's row, pin that with a negative
control and return the skip code. Record what the saved gfx1035 rows show
about the rule in the debt entry.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Version 50 is skipped, so a request with that number is refused instead
of being read in the version 49 layout.
The one-lane tessellation evaluation debt entry now states that only a
v_readlane_b32 of a constant lane throws: a lane selector held in a
register is not checked and reads the invocation's own value, as on the
vertex path.
MoltenVK and lavapipe leave the tessellation evaluation stage out of
subgroupSupportedStages, so the driver's shader validation refuses every
domain program that declares GroupNonUniform ("subgroup capability 61 is
unsupported for shader stage 4"). Gran Turismo 7 stops there on macOS at
the Used Car dealership.
The device target now records whether the tessellation evaluation stage
has subgroups. When it does not, tessellation evaluation programs outside
the mesh path get a host subgroup width of 1 and the one-lane rules that
vertex programs already use without vertex subgroups: the lane id is 0,
a ballot is the invocation's own bit, a shuffle returns the invocation's
value and an elect is true. Reads of other lanes still throw. Devices
with tessellation evaluation subgroups emit the same SPIR-V as before.
The request serialization moves to version 51.
The four-mode matrix of the FLOAT_MODE f16/f64 denormal field was pinned from the
RDNA2 ISA and from LLVM but never measured on hardware. Measured on RDNA2 (gfx1036,
AMD Windows driver 31.0.22044.1) with the hardware oracle over the 22-value f64 edge
set of VopcCompareF64 as all 484 operand pairs, with the 16 v_cmp_*_f64 predicates,
at IEEE off and on and each f16/f64 denormal mode 0 to 3: modes 0 and 2 flush, modes
1 and 3 keep, the IEEE bit changes neither, and class compares select from the
pre-flush bits. The sign of the flushed zero is not observable by a compare. The
PS5's gfx1013 stays unmeasured.
Carry the RoundEven and unordered NOT_EQUAL fixes from #907, with
ThisIsAkill's invitation, onto the current constant-zero comparison path.
Keep TRUNC_COORD accepted for that path and retain the newer format rules.
Exercise array rounding through converted unorm sampling, where selecting
the wrong layer changes the result. Preserve zero comparisons for half-float
NaNs, signed zero, GREATER, NOT_EQUAL and TRUNC_COORD. Record the inherited
RDNA2 measurement basis and the limits of these host tests.
Co-Authored-By: Akhil Moola <[email protected]>
Co-Authored-By: Claude Opus 5.5 <[email protected]>
A PS4 Pro (GCN, firmware 10.71) returns the input times 0x40c90fd5 for
every v_sin_f32 input below 0x39c00000 (1.5 x 2^-12 of a turn) and for
none at or above it, over 12,288 consecutive inputs of each sign across
that boundary and 65,536 random inputs from 2^-24 to 1 turn. The linear
band from 909281c994 ends at 2^-12, as measured on RDNA2, so PS4 guest
shaders took the driver sine or the series in [2^-12, 1.5 x 2^-12),
where the PS4 is 5 ULP away from the true sine.
PS4 guest shaders now keep the integer band of v_sin_f32 up to
0x39c00000. The half- and quarter-turn bands keep 2^-12: there the PS4
is within 6 ULP of the f32 2pi term and is not linear. PS5 shaders are
unchanged.
GcnSinNearZero runs a GCN compute kernel over PS4-measured inputs; it
fails without the change (0x39bf48b8 gives 0x3b163be8, the PS4 returns
0x3b163bed).
Co-Authored-By: Claude Opus 5.5 <[email protected]>
An image-table offset that is scaled by a constant stride before v_readfirstlane is recognized as a constant-stride column through selects whose condition the active mask implies. Runtime SRT evaluation supports unsigned greater-than-or-equal comparisons, uniform selected components of constructed U32x4 values and known active-mask conjuncts in nested selects. Image dimension queries stay in GPU IR and variable scales are not constant-stride columns.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
On NVIDIA's proprietary driver, function arrays that live in local memory
and are read under a data-dependent branch return wrong values in
subgroups 1-3 of a mesh workgroup; subgroup 0 is correct. A wave64
geometry program whose relative addressing keeps its VGPRs in the vector
window therefore loses register writes in every wave but the first. In
the clipping geometry program of Sony's PS5 PSP emulator (PPSA07550) the
empty waves never cleared their candidate primitive slots and wrote
degenerate triangles over wave 0's, so the 3D menu drew spikes.
On that driver a mesh program's window now lives in a device-local
storage buffer of 256 workgroup slots of 65536 dwords, claimed through a
per-slot lock and released after the final barrier. The pool is created
before the first draw that uses it records anything, and its header is
zeroed in a batch of its own that is submitted and waited for; the pool
is published only after that wait, and a failure releases it. Direct
register accesses keep one function variable per register; a direct
store also writes the buffer when a buffer read can see it, relative
reads load the buffer, relative writes store only to it, and a direct
read that may follow a relative write loads the buffer and refreshes the
variable. A buffer entry is zeroed only when a buffer read can see it
before a write. APS5_NO_MESH_WINDOW_BUFFER=1 keeps the arrays.
On a one-lane wave (vertex and local programs without vertex subgroups,
merged hull programs), a wave64 f32 max half-wave scan threw at its
v_permlanex16_b32. When the scan's lane 31 and 63 reads only elect,
through v_cmpx_eq_f32 against each lane's own key, the lanes that
buffer_atomic_umax or smax that maximum at a wave-uniform address with an
unused result, each invocation now takes its own key: every active lane
writes it, and memory ends with the wave's maximum because the keys are
proven non-negative and not NaN. The permutation, whose value then
reaches no other result, keeps its own value.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The barycentric tessellation path refused any draw with the primitive
restart bit set. A non-indexed strip ignores the bit, and on a device
without VK_EXT_primitive_topology_list_restart a list never restarts on
the host, since its indices are compacted on the CPU first, so both now
take the patches. Indexed strips with primitive restart still throw,
now also in Graphics::Draw, which knows the draw is indexed.
Patch-list pipelines never enable primitive restart, which Vulkan does not
allow for them without primitiveTopologyPatchListRestart.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The _a sample forms only change how dword 3 of the S# is read, so an image_sample_a of a 2D MSAA T# now takes the same sample-0 path as image_sample: the tracker leaves the adjust flag out of its plain-sample check. Ghost of Tsushima's pixel shader 0x20054f4e00 samples its two-sample checkerboard depth this way and stopped with "image descriptor is incompatible with the static runtime image interface".
Co-Authored-By: Claude Opus 5.5 <[email protected]>
A read at a negative offset from a pointer the walker loaded from guest
memory (a null pointer behind a guarded branch, offset -4) wrapped below
zero in AddSignedAddress, and the walk threw "cannot evaluate" instead of
recording the read as inaccessible. Uncharted: The Lost Legacy threw it
while loading its first level. The read is now recorded as an SRT poison
at its address wrapped to 48 bits, like any other unreadable address, so
the binding faults only if the shader takes that path.
verifyGuardedNullPointers gains the case for both branch outcomes; it
throws the title's error without the change.
AI-assisted: yes
A buffer V# whose TYPE is not 0 threw "buffer descriptor uses an
unsupported type" for every access. Measured on a PS5 (CFI-1115B,
firmware 12.20): through a V# with TYPE 2 or 3 and FORMAT 0 or a valid
format, buffer_store_dword and buffer_store_format_x write nothing and
don't fault, so a buffer a shader only stores to through one is bound as
a null V#. Loads and atomics through those V#s leave the destination VGPR
unchanged, which a null V# can't reproduce, so they still throw. Through
a TYPE 0, FORMAT 0 V#, vector loads return 0 and stores are dropped, and
those buffers are bound as a null V# too. TYPE 1 faults the GPU for every
access measured and keeps throwing.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
This reverts merge 7fc0ae6008. On NVIDIA, where helper lanes take part in ballots, clearing helper bits from every pixel ballot breaks derivatives along triangle edges (bright lines and specks on a cloud surface in PPSA21564). See the report on #11199.
v_fma_f32, v_fmac_f32, v_fmamk_f32 and v_fmaak_f32 threw "f32 denormal
mode 2 is not implemented" whenever FLOAT_MODE flushed f32 denormal
inputs but kept denormal results.
On RDNA2 (gfx1036) at round to nearest even, mode 2 flushes the inputs
and rounds the fused result once with gradual underflow, which the host's
Fma gives under DenormPreserve 32. The translation now matches all 5,596
measured triples for the four forms at IEEE 0 and 1. Mode 1 keeps
throwing: there the hardware flushes a result that is tiny after rounding
with an unbounded exponent even when the addend is nonzero.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
All four threw "f32 denormal mode N is not implemented" whenever
FLOAT_MODE kept only one side of the f32 denormals.
On RDNA2 (gfx1036), in every f32 round mode and at IEEE 0 and 1, mode 2
gives the results of mode 0 and mode 1 those of mode 3 with a denormal
result flushed, which only v_fract_f32 of a positive denormal produces.
The translation now matches all 118 measured inputs in modes 1 and 2.
Mode 1 of the three that run host float operations on a kept denormal
needs DenormPreserve 32, as v_min_f32 does.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Both threw "f32 denormal mode N is not implemented" whenever FLOAT_MODE
kept only one side of the f32 denormals, so any LLVM-compiled f32
division in such a shader failed to translate.
On RDNA2 (gfx1036) at round to nearest even, v_div_fixup_f32 follows bit
0 of the field, and v_div_scale_f32 flushes its inputs in mode 2 as in
mode 0 and in mode 1 keeps them and flushes a denormal result, with the
VCC of mode 3. The translation now matches all 2,304 measured rows in
modes 1 and 2 at IEEE 0 and 1. Directed rounding still throws, as an
underflowing v_div_fixup_f32 result rounds to the smallest denormal there.
Division and F32DenormalFlush no longer require modes 1 and 2 to be
refused; Division checks v_div_scale_f32 in them against its measured
vectors instead.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Dean