v_cvt_f32_ubyte0 to v_cvt_f32_ubyte3 take byte N of source 0 after
SRC0_SEL and SRC0_SEXT select and extend it, as measured with the
hardware oracle on RDNA2 (gfx1036) for all seven source selects with
and without SRC0_SEXT. The test checked four combinations derived from
the ISA guide; it now checks every combination against the measured
results, and the debt entry keeps only what is not measured: gfx1013.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The f32 conversions that only flush their inputs follow bit 0 of the
FLOAT_MODE f32 denormal field, as the f32 compares do: mode 1 keeps
denormal inputs like mode 3 and mode 2 flushes them like mode 0.
v_cvt_pk_u8_f32 also follows a round mode set at run time.
Measured on RDNA2 (gfx1036) with the hardware oracle.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
The driver refuses a draw that enables a cull distance when the device
has no shaderCullDistance, and agc_driver_vertex_clip_cull_distances,
agc_driver_vertex_clip_cull_draw (with and without the draw key) and
agc_driver_vertex_user_data_tail ran their cull distance cases anyway,
so on MoltenVK all four failed at that refusal. They now skip only
those cases when the target lacks CapabilityCullDistance, as they
already skip the mesh case without VK_EXT_mesh_shader, and the shader
debt entry records the refusal.
image_get_resinfo returns 0 in its third component when the instruction's
DIM has no layers (1D, 2D, 2D MSAA) and the T# is not 3D, as measured on
RDNA 2 in #7550. Keep 1D-array T#s on their first layer and MSAA T#s
refused, and record the unmeasured forms in the shader debt file.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Table T#s keyed at runtime feeding image_atomic64_* now lower to
OpAtomic* on the table Atomic64View instead of faulting, mirroring
the 32-bit path: gate, dedup identity, binding flags and view
selection. Packed formats and BY element counts still fault; hosts
need VK_FORMAT_FEATURE_STORAGE_IMAGE_ATOMIC_BIT for the view format.
v_rcp_f32 and v_rcp_iflag_f32 lower to the driver's 1/x, whose low bits
differ from the console's on NVIDIA and Intel. With APS5_EXACT_RCP set,
normal inputs with normal results take the RDNA reciprocal datapath
instead: a cubic over 32 segments of the mantissa in 32-bit integer
arithmetic, the linear term rounded to nearest even, and a 2,761-entry
table of one-ULP corrections, looked up only when the dropped bits fall
next to the rounding cut (6.25 % of inputs). This reproduces all 2^23
mantissas of an RDNA2 (gfx1031) sweep. Other inputs keep 1/x.
It is off by default: the tables add about 13k SPIR-V words to each
shader that uses it.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_017EjjFU1FjMR11oWDYs8UMo
Table T#s keyed at runtime no longer fault on image_atomic_*32: the
table operation stays supported, elements carry the atomic flag through
dedup into the descriptor binding, and the table path binds AtomicView
like the direct path. 64-bit atomics stay unsupported, packed and BY
formats stay unsupported, and the debt entry records the relaxed
Device-scoped emission and the remaining gaps.
The shader float mode entry said "Other f64 arithmetic does not model
these denormal controls". On main, v_add_f64, v_mul_f64, v_floor_f64,
v_ceil_f64, v_fract_f64, v_frexp_mant_f64, v_frexp_exp_i32_f64,
v_div_fixup_f64, the f64 compares and ds_min/max/cmpst_f64 read the
f16/f64 denormal field, and each has its own entry. The sentence now
names the f64 arithmetic whose translation still does not read it.
The v_floor_f64 entry said its modifier run used 16 of the 23 measured
values. The run's list holds 13 of them plus -1.5, 2.75 and 1 - 2^-53.
Co-Authored-By: Claude <[email protected]>
The recompiler orders an LDS atomic, and the compare-exchange loop that
writes a byte or a halfword of LDS (ds_write_b8/b16), with a
workgroup-scope OpMemoryBarrier after the update. AMD's proprietary
Windows driver 32.0.21042.62 (Radeon 0x13c0, RDNA 2) compiles that
memory barrier to s_barrier, as the code objects in its pipeline cache
show. Such updates usually sit in branches that only some waves of a
workgroup take, so those waves execute extra s_barriers, which pair
with the other waves' barriers, and the other waves read LDS before it
is written. An OpMemoryBarrier is not an execution barrier and SPIR-V
allows it in non-uniform control flow, so the SPIR-V is valid; a
device-scope OpMemoryBarrier compiles to GL0 and GL1 cache
invalidations without s_barrier there.
PS5LM Plus (PPSA99581, llama.cpp's Vulkan backend) drifted into
garbage on that driver with flash attention on. Its flash-attention
shader stores two halfwords to LDS in a branch that two of its four
waves take, inside the KV loop. The driver's code had 23 s_barrier for
the guest's 21; a replay of the dispatch differed from NVIDIA in 159
words, up to 1.7e38, and now has 21 and differs only in the last bit
of 9 words.
On that driver the fence is now device scope, which orders everything
the workgroup-scope fence did. Other drivers keep the workgroup scope.
The flag is part of the shader cache key, and agc_shader_replay takes
--device-scope-lds-memory-barriers to replay a request the way that
driver compiles it. The LDS update helper already fences, so the
second, identical fence after it in ds_min/max_f32 and the other
read-modify-write LDS operations is dropped.
agc_driver_lds_subword_store_branch stores a halfword to LDS in a
branch that waves 0-1 of four take, delays those waves and then
exchanges LDS slots across one s_barrier. Before, thread 64 read a
stale slot on the AMD driver; it passes on AMD and NVIDIA now.
agc_subgroup_barrier checks the driver quirk and that ds_write_b16,
ds_add_u32 and ds_max_f32 each emit one fence of the expected scope.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01BM2kfDbr6MydxsfTckZJDR
Dean