AnyPS5

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mugurc 100148f762 fix(tests): expect the SSE traps the host keeps in the floating-point trap checks

The trap checks unmask exceptions with feenableexcept and its relatives
and expect MXCSR to hold the new masks, and the enable and disable
results to report the traps enabled on both units. Under Rosetta 2
MXCSR keeps its six exception masks set, so no SSE trap is ever enabled
and every result reports none. The test now asks the host once whether
it keeps an unmasked MXCSR exception and, where it does not, expects
all six SSE masks set and no trap on both units; on other hosts the
expectations are the same as before. A debt entry records that the
trap functions change only the x87 masks under Rosetta.

2026-10-22 13:00:10 +03:00

debt

fix(tests): expect the SSE traps the host keeps in the floating-point trap checks

2026-10-22 13:00:10 +03:00

ARCHITECTURE.md

Merge pull request #9203 from mazen320/docs/entry-register-contract

2026-10-21 20:22:04 +02:00

BUILD.md

feat(windows): support MSYS2 GCC runtime builds

2026-10-21 20:29:55 -07:00

CONVENTIONS.md

docs(dev): require a HostWrite bracket around host writes into guest memory