3 people 56ea14f44c fix(agc): an HTILE fill covers a depth surface only over its whole pipe-aligned metadata ...

A fill was taken to cover the surface when it spanned ceil(w/8)*ceil(h/8)*4 bytes, a linear HTILE layout. In
the pipe-aligned SW_64KB_Z_X layout a surface's HTILE words lie across a 32 KiB metadata block per 1024x512
pixels (AMD PAL gfx10 addrlib: a 16x16 surface has a valid word at offset 260), so a fill of the linear size
cleared tiles it never wrote. HtileMetadataBytes gives that extent; the fast clear tests fill it (the compute
fixture now dispatches one group per KiB with TGID_X).

Reported with a PAL reproducer by @Amoenus.

Co-Authored-By: Amoenus <[email protected]>
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>

2026-10-11 10:19:53 +02:00

..

ARCHITECTURE.md

docs(architecture): user-data callees; drop code comment

2026-10-11 09:59:27 +02:00

BUILD.md

fix(agc): report a refused queue worker priority as a driver failure and reject unknown APS5_THREAD_PRIORITY values

2026-10-10 12:23:12 -06:00

CONVENTIONS.md

refactor(docs): separated user and dev in docs + compatibility file

2026-09-28 22:58:17 +03:00

HW_ORACLE.md

feat(shader): follow FP16_OVFL in every f16 result

2026-10-10 04:32:38 -03:00

PROGRESS.md

fix(progress): link include-shared libraries and label empty ones

2026-10-10 08:49:58 +02:00

TechnicalDebt.md

fix(agc): an HTILE fill covers a depth surface only over its whole pipe-aligned metadata

2026-10-11 10:19:53 +02:00