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A raise delivered some other way (the deliverer sampled the target in guest code and redirected it) disarms the return breakpoint by clearing DR0 and DR7 with SetThreadContext. When the target reaches the armed return address at the same moment, the debug exception is already raised but the context Windows hands to the handler carries the cleared registers: DR0, DR6 and DR7 are 0. ReturnBreakHandler required DR6.B0, so it declined, and the unhandled EXCEPTION_SINGLE_STEP ended the process with 0x80000004. Under parallel load guest_raise_in_host_code failed this way 18 times in 900 runs; a diagnostic in the declining branch showed every failure at an address armed earlier on that same thread, with no live return break, DR0 = DR6 = DR7 = 0 and TF clear. The ring of armed addresses now records the thread with each address. A single-step that has TF clear, no breakpoint hit in DR6 and no breakpoint enabled in DR7, at an address this library armed on the faulting thread, is taken as that disarmed return breakpoint and continues; any other single-step is left to the next handler. A DR0 hit is likewise matched against the addresses armed on the faulting thread. Co-Authored-By: Claude Opus 5.5 <[email protected]>