mirror of
https://github.com/boykopovar/AnyPS5.git
synced 2026-11-06 13:30:00 +00:00
Jevro1337andClaude Opus 5.5
ab363feecc
A handler installed for SIGILL, SIGFPE, SIGBUS or SIGSEGV now receives the faults raised in title code instead of the process ending, with mc_trapno, mc_addr and mc_err filled as FreeBSD 11's amd64 trap() does. On Windows the crash reporter's vectored handler offers unclaimed faults to libkernel, which redirects the thread to a stub that runs the handler outside the exception dispatcher; on Linux chained host signal handlers classify faults by REG_TRAPNO. Co-Authored-By: Claude Opus 5.5 <[email protected]>
460 lines
16 KiB
C++
460 lines
16 KiB
C++
#include "SceTypes.hpp"
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#include "prx/libc/include/GuestWriteWatch.hpp"
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#include <atomic>
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#include <climits>
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#include <cstddef>
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#include <cstdint>
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#include <cstdio>
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#include <cstdlib>
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#include <cstring>
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#include <thread>
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#ifdef _WIN32
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#include <windows.h>
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#else
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#include <sys/mman.h>
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#endif
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extern "C" {
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int APS5_VABI sceKernelInstallExceptionHandler(int signum, void* handler);
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int APS5_VABI sceKernelRemoveExceptionHandler(int signum);
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[[noreturn]] void APS5_VABI longjmp_nid_postfix(void* buffer, int value);
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}
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struct RegisterState {
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std::uint8_t vectorIn[32];
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std::uint8_t vectorOut[32];
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std::uint32_t avx;
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std::uint32_t padding;
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std::uint64_t r12;
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std::uint64_t r13;
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};
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static_assert(offsetof(RegisterState, vectorOut) == 32 && offsetof(RegisterState, avx) == 64 && offsetof(RegisterState, r12) == 72 && offsetof(RegisterState, r13) == 80);
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extern "C" {
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std::uint64_t APS5_VABI FaultTestRead(std::uintptr_t address);
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void FaultTestReadSite();
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void FaultTestReadResume();
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std::uint64_t APS5_VABI FaultTestWrite(std::uintptr_t address, std::uint64_t value);
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void FaultTestWriteSite();
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void FaultTestWriteResume();
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std::uint64_t APS5_VABI FaultTestIllegal();
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void FaultTestIllegalSite();
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void FaultTestIllegalResume();
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std::uint64_t APS5_VABI FaultTestDivide(std::int32_t dividend, std::int32_t divisor);
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void FaultTestDivideSite();
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void FaultTestDivideResume();
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void APS5_VABI FaultTestRegisters(std::uintptr_t address, RegisterState* state);
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void FaultTestRegistersSite();
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void FaultTestRegistersResume();
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std::uint64_t APS5_VABI FaultTestJump(std::uintptr_t address, void* buffer);
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void FaultTestJumpSite();
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std::uint64_t APS5_VABI FaultTestSimdDivide();
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void FaultTestSimdDivideSite();
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void FaultTestSimdDivideResume();
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}
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asm(".text\n"
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".globl FaultTestRead\n"
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"FaultTestRead:\n"
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" xorl %eax, %eax\n"
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".globl FaultTestReadSite\n"
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"FaultTestReadSite:\n"
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" movq (%rdi), %rax\n"
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".globl FaultTestReadResume\n"
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"FaultTestReadResume:\n"
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" ret\n"
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".globl FaultTestWrite\n"
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"FaultTestWrite:\n"
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" xorl %eax, %eax\n"
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".globl FaultTestWriteSite\n"
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"FaultTestWriteSite:\n"
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" movq %rsi, (%rdi)\n"
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".globl FaultTestWriteResume\n"
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"FaultTestWriteResume:\n"
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" ret\n"
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".globl FaultTestIllegal\n"
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"FaultTestIllegal:\n"
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" xorl %eax, %eax\n"
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".globl FaultTestIllegalSite\n"
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"FaultTestIllegalSite:\n"
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" ud2\n"
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".globl FaultTestIllegalResume\n"
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"FaultTestIllegalResume:\n"
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" ret\n"
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".globl FaultTestDivide\n"
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"FaultTestDivide:\n"
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" movl %edi, %eax\n"
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" cltd\n"
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".globl FaultTestDivideSite\n"
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"FaultTestDivideSite:\n"
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" idivl %esi\n"
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".globl FaultTestDivideResume\n"
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"FaultTestDivideResume:\n"
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" ret\n"
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".globl FaultTestRegisters\n"
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"FaultTestRegisters:\n"
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" pushq %r12\n"
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" pushq %r13\n"
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" pushq %rbx\n"
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" movq %rsi, %rbx\n"
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" movabsq $0x1111222233334444, %r12\n"
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" movabsq $0x5555666677778888, %r13\n"
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" cmpl $0, 64(%rbx)\n"
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" je 1f\n"
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" vmovdqu 0(%rbx), %ymm8\n"
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" jmp 2f\n"
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"1:\n"
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" movdqu 0(%rbx), %xmm8\n"
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"2:\n"
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".globl FaultTestRegistersSite\n"
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"FaultTestRegistersSite:\n"
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" movq (%rdi), %rax\n"
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".globl FaultTestRegistersResume\n"
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"FaultTestRegistersResume:\n"
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" movq %r12, 72(%rbx)\n"
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" movq %r13, 80(%rbx)\n"
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" cmpl $0, 64(%rbx)\n"
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" je 3f\n"
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" vmovdqu %ymm8, 32(%rbx)\n"
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" vzeroupper\n"
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" jmp 4f\n"
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"3:\n"
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" movdqu %xmm8, 32(%rbx)\n"
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"4:\n"
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" popq %rbx\n"
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" popq %r13\n"
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" popq %r12\n"
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" ret\n"
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".globl FaultTestJump\n"
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"FaultTestJump:\n"
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" pushq %rbx\n"
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" pushq %rbp\n"
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" pushq %r12\n"
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" pushq %r13\n"
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" pushq %r14\n"
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" pushq %r15\n"
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" subq $8, %rsp\n"
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" leaq 5f(%rip), %rax\n"
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" movq %rax, 0(%rsi)\n"
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" movq %rbx, 8(%rsi)\n"
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" movq %rsp, 16(%rsi)\n"
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" movq %rbp, 24(%rsi)\n"
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" movq %r12, 32(%rsi)\n"
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" movq %r13, 40(%rsi)\n"
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" movq %r14, 48(%rsi)\n"
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" movq %r15, 56(%rsi)\n"
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" stmxcsr 64(%rsi)\n"
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" fnstcw 68(%rsi)\n"
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".globl FaultTestJumpSite\n"
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"FaultTestJumpSite:\n"
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" movq (%rdi), %rax\n"
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" xorl %eax, %eax\n"
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"5:\n"
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" addq $8, %rsp\n"
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" popq %r15\n"
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" popq %r14\n"
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" popq %r13\n"
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" popq %r12\n"
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" popq %rbp\n"
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" popq %rbx\n"
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" ret\n"
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".globl FaultTestSimdDivide\n"
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"FaultTestSimdDivide:\n"
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" subq $8, %rsp\n"
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" stmxcsr (%rsp)\n"
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" movl $0x1d80, 4(%rsp)\n"
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" ldmxcsr 4(%rsp)\n"
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" movl $1, %eax\n"
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" cvtsi2ss %eax, %xmm0\n"
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" xorps %xmm1, %xmm1\n"
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" xorl %eax, %eax\n"
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".globl FaultTestSimdDivideSite\n"
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"FaultTestSimdDivideSite:\n"
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" divss %xmm1, %xmm0\n"
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".globl FaultTestSimdDivideResume\n"
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"FaultTestSimdDivideResume:\n"
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" ldmxcsr (%rsp)\n"
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" addq $8, %rsp\n"
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" ret\n");
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static constexpr int GUEST_SIGILL = 4;
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static constexpr int GUEST_SIGFPE = 8;
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static constexpr int GUEST_SIGBUS = 10;
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static constexpr int GUEST_SIGSEGV = 11;
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static constexpr std::uint32_t T_PRIVINFLT = 1;
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static constexpr std::uint32_t T_PROTFLT = 9;
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static constexpr std::uint32_t T_PAGEFLT = 12;
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static constexpr std::uint32_t T_DIVIDE = 18;
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static constexpr std::uint32_t T_XMMFLT = 29;
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static constexpr std::uint64_t PGEX_P = 0x1;
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static constexpr std::uint64_t PGEX_W = 0x2;
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static constexpr std::uint64_t PGEX_U = 0x4;
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static constexpr std::size_t RbxOffset = 0x80;
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static constexpr std::size_t RaxOffset = 0x78;
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static constexpr std::size_t R12Offset = 0xa0;
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static constexpr std::size_t R13Offset = 0xa8;
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static constexpr std::size_t TrapnoOffset = 0xc0;
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static constexpr std::size_t AddrOffset = 0xc8;
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static constexpr std::size_t ErrOffset = 0xd8;
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static constexpr std::size_t RipOffset = 0xe0;
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static constexpr std::size_t Xmm8Offset = 0x140 + 160 + 8 * 16;
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static constexpr std::uintptr_t NullAddress = 0x10;
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static constexpr std::uintptr_t NonCanonicalAddress = 0x8000000000000000ULL;
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static constexpr std::uint64_t Resumed = 0x600dcafe0000beefULL;
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static constexpr std::uint64_t PatchedR12 = 0x5a5a1234abcd0001ULL;
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static constexpr int JumpValue = 7;
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static constexpr std::size_t PageBytes = 4096;
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static constexpr std::size_t WatchedBytes = 65536;
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enum class Mode { Resume, Registers, Nested, Jump };
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static void Require(bool value) { if (!value) std::abort(); }
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template <typename TValue>
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static TValue Field(void* context, std::size_t offset) {
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TValue value{};
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std::memcpy(&value, static_cast<unsigned char*>(context) + offset, sizeof(value));
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return value;
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}
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template <typename TValue>
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static void SetField(void* context, std::size_t offset, TValue value) {
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std::memcpy(static_cast<unsigned char*>(context) + offset, &value, sizeof(value));
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}
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static std::uintptr_t Address(void (*label)()) {
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return reinterpret_cast<std::uintptr_t>(label);
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}
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struct Expected {
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int signum;
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std::uint32_t trapno;
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std::uint64_t addr;
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std::uintptr_t site;
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std::uintptr_t resume;
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};
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static Mode mode = Mode::Resume;
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static Expected expected{};
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static std::atomic<int> calls{0};
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static std::atomic<int> nestedCalls{0};
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static std::uint64_t observedErr = 0;
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static std::atomic<std::thread::id> handlerThread;
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static RegisterState* registerState = nullptr;
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alignas(16) static std::uint8_t jumpBuffer[128];
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static void Check(int signum, void* context, const Expected& want) {
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Require(signum == want.signum);
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Require(Field<std::uint32_t>(context, TrapnoOffset) == want.trapno);
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Require(Field<std::uint64_t>(context, AddrOffset) == want.addr);
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Require(Field<std::uint64_t>(context, RipOffset) == want.site);
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}
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static void Resume(void* context, std::uintptr_t resume) {
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SetField<std::uint64_t>(context, RipOffset, resume);
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SetField<std::uint64_t>(context, RaxOffset, Resumed);
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}
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static void APS5_VABI IllegalHandler(int signum, void* context) {
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if (mode == Mode::Nested && calls.load() == 1) {
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Check(signum, context, {GUEST_SIGILL, T_PRIVINFLT, 0, Address(FaultTestIllegalSite), 0});
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nestedCalls.fetch_add(1);
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Resume(context, Address(FaultTestIllegalResume));
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return;
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}
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Check(signum, context, expected);
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calls.fetch_add(1);
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Resume(context, expected.resume);
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}
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static void APS5_VABI Handler(int signum, void* context) {
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Check(signum, context, expected);
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observedErr = Field<std::uint64_t>(context, ErrOffset);
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handlerThread.store(std::this_thread::get_id());
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calls.fetch_add(1);
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if (mode == Mode::Jump) longjmp_nid_postfix(jumpBuffer, JumpValue);
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if (mode == Mode::Nested) Require(FaultTestIllegal() == Resumed);
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if (mode == Mode::Registers) {
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Require(Field<std::uint64_t>(context, R13Offset) == 0x5555666677778888ULL);
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Require(Field<std::uint64_t>(context, RbxOffset) == reinterpret_cast<std::uint64_t>(registerState));
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Require(std::memcmp(static_cast<unsigned char*>(context) + Xmm8Offset, registerState->vectorIn, 16) == 0);
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SetField<std::uint64_t>(context, R12Offset, PatchedR12);
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SetField<std::uint64_t>(context, RipOffset, expected.resume);
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if (registerState->avx != 0) asm volatile("vzeroall" ::: "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15");
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return;
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}
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Resume(context, expected.resume);
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}
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static void Arm(Mode next, const Expected& want) {
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mode = next;
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expected = want;
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calls.store(0);
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nestedCalls.store(0);
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observedErr = 0;
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}
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static void* Pages(std::size_t bytes, bool writable) {
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#ifdef _WIN32
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void* pages = VirtualAlloc(nullptr, bytes, MEM_RESERVE | MEM_COMMIT, writable ? PAGE_READWRITE : PAGE_READONLY);
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Require(pages != nullptr);
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#else
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void* pages = mmap(nullptr, bytes, writable ? PROT_READ | PROT_WRITE : PROT_READ, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
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Require(pages != MAP_FAILED);
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#endif
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return pages;
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}
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static void FreePages(void* pages, std::size_t bytes) {
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#ifdef _WIN32
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(void)bytes;
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Require(VirtualFree(pages, 0, MEM_RELEASE) != 0);
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#else
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Require(munmap(pages, bytes) == 0);
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#endif
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}
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static void TestRead() {
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Arm(Mode::Resume, {GUEST_SIGSEGV, T_PAGEFLT, NullAddress, Address(FaultTestReadSite), Address(FaultTestReadResume)});
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Require(FaultTestRead(NullAddress) == Resumed);
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Require(calls.load() == 1);
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Require((observedErr & PGEX_U) != 0);
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Require((observedErr & (PGEX_W | PGEX_P)) == 0);
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Require(handlerThread.load() == std::this_thread::get_id());
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}
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static void TestWriteToReadOnly() {
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void* page = Pages(PageBytes, false);
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const auto address = reinterpret_cast<std::uintptr_t>(page) + 8;
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Require(*reinterpret_cast<volatile std::uint64_t*>(address) == 0);
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Arm(Mode::Resume, {GUEST_SIGSEGV, T_PAGEFLT, address, Address(FaultTestWriteSite), Address(FaultTestWriteResume)});
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Require(FaultTestWrite(address, 1) == Resumed);
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Require(calls.load() == 1);
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Require((observedErr & (PGEX_U | PGEX_W | PGEX_P)) == (PGEX_U | PGEX_W | PGEX_P));
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Require(*reinterpret_cast<volatile std::uint64_t*>(address) == 0);
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FreePages(page, PageBytes);
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}
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static void TestIllegal() {
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Arm(Mode::Resume, {GUEST_SIGILL, T_PRIVINFLT, 0, Address(FaultTestIllegalSite), Address(FaultTestIllegalResume)});
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Require(FaultTestIllegal() == Resumed);
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Require(calls.load() == 1);
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}
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static void TestDivide() {
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Arm(Mode::Resume, {GUEST_SIGFPE, T_DIVIDE, 0, Address(FaultTestDivideSite), Address(FaultTestDivideResume)});
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Require(FaultTestDivide(1, 0) == Resumed);
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Require(calls.load() == 1);
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Arm(Mode::Resume, {GUEST_SIGFPE, T_DIVIDE, 0, Address(FaultTestDivideSite), Address(FaultTestDivideResume)});
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Require(FaultTestDivide(INT_MIN, -1) == Resumed);
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Require(calls.load() == 1);
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}
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static void TestSimdDivide() {
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Arm(Mode::Resume, {GUEST_SIGFPE, T_XMMFLT, 0, Address(FaultTestSimdDivideSite), Address(FaultTestSimdDivideResume)});
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Require(FaultTestSimdDivide() == Resumed);
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Require(calls.load() == 1);
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}
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static void TestNonCanonical() {
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Arm(Mode::Resume, {GUEST_SIGBUS, T_PROTFLT, 0, Address(FaultTestReadSite), Address(FaultTestReadResume)});
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Require(FaultTestRead(NonCanonicalAddress) == Resumed);
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Require(calls.load() == 1);
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}
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static void TestRegisters() {
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RegisterState state{};
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for (std::size_t i = 0; i < sizeof(state.vectorIn); ++i) state.vectorIn[i] = static_cast<std::uint8_t>(0xa0 + i);
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state.avx = __builtin_cpu_supports("avx") ? 1 : 0;
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registerState = &state;
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Arm(Mode::Registers, {GUEST_SIGSEGV, T_PAGEFLT, NullAddress, Address(FaultTestRegistersSite), Address(FaultTestRegistersResume)});
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FaultTestRegisters(NullAddress, &state);
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Require(calls.load() == 1);
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Require(state.r12 == PatchedR12);
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Require(state.r13 == 0x5555666677778888ULL);
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Require(std::memcmp(state.vectorOut, state.vectorIn, state.avx != 0 ? 32 : 16) == 0);
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registerState = nullptr;
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}
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static void TestNested() {
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Arm(Mode::Nested, {GUEST_SIGSEGV, T_PAGEFLT, NullAddress, Address(FaultTestReadSite), Address(FaultTestReadResume)});
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Require(FaultTestRead(NullAddress) == Resumed);
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Require(calls.load() == 1);
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Require(nestedCalls.load() == 1);
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}
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static void TestJumpOut() {
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for (int round = 0; round < 3; ++round) {
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Arm(Mode::Jump, {GUEST_SIGSEGV, T_PAGEFLT, NullAddress, Address(FaultTestJumpSite), 0});
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Require(FaultTestJump(NullAddress, jumpBuffer) == JumpValue);
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Require(calls.load() == 1);
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}
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TestRead();
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}
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static void TestWatchedStore() {
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using namespace GuestWriteWatch;
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if (!GuestWriteWatchAvailable_nid_postfix()) {
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std::puts("write watch unavailable: watched store not tested");
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return;
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}
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void* watched = Pages(WatchedBytes, true);
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const auto begin = reinterpret_cast<std::uintptr_t>(watched);
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GuestWriteWatchRegister_nid_postfix(watched, WatchedBytes);
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const auto collect = [&] {
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std::uintptr_t written = 0;
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Require(GuestWriteWatchCollect_nid_postfix(begin, WatchedBytes, [](void* context, std::uintptr_t first, std::uintptr_t end) {
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auto& address = *static_cast<std::uintptr_t*>(context);
|
|
if (address == 0) address = first;
|
|
(void)end;
|
|
}, &written));
|
|
return written;
|
|
};
|
|
collect();
|
|
Require(collect() == 0);
|
|
const auto address = begin + WatchedBytes / 2 + 8;
|
|
Arm(Mode::Resume, {GUEST_SIGSEGV, T_PAGEFLT, address, Address(FaultTestWriteSite), Address(FaultTestWriteResume)});
|
|
Require(FaultTestWrite(address, 5) == 0);
|
|
Require(calls.load() == 0);
|
|
Require(*reinterpret_cast<volatile std::uint64_t*>(address) == 5);
|
|
const auto written = collect();
|
|
Require(written != 0 && written <= address && address < begin + WatchedBytes);
|
|
GuestWriteWatchUnregister_nid_postfix(watched, WatchedBytes);
|
|
FreePages(watched, WatchedBytes);
|
|
}
|
|
|
|
static void TestOtherThread() {
|
|
Arm(Mode::Resume, {GUEST_SIGSEGV, T_PAGEFLT, NullAddress, Address(FaultTestReadSite), Address(FaultTestReadResume)});
|
|
std::thread::id worker;
|
|
std::uint64_t result = 0;
|
|
std::thread thread([&] {
|
|
worker = std::this_thread::get_id();
|
|
result = FaultTestRead(NullAddress);
|
|
});
|
|
thread.join();
|
|
Require(result == Resumed);
|
|
Require(calls.load() == 1);
|
|
Require(handlerThread.load() == worker);
|
|
}
|
|
|
|
int main() {
|
|
__builtin_cpu_init();
|
|
Require(sceKernelInstallExceptionHandler(GUEST_SIGSEGV, reinterpret_cast<void*>(&Handler)) == 0);
|
|
Require(sceKernelInstallExceptionHandler(GUEST_SIGBUS, reinterpret_cast<void*>(&Handler)) == 0);
|
|
Require(sceKernelInstallExceptionHandler(GUEST_SIGFPE, reinterpret_cast<void*>(&Handler)) == 0);
|
|
Require(sceKernelInstallExceptionHandler(GUEST_SIGILL, reinterpret_cast<void*>(&IllegalHandler)) == 0);
|
|
TestRead();
|
|
TestWriteToReadOnly();
|
|
TestIllegal();
|
|
TestDivide();
|
|
TestSimdDivide();
|
|
TestNonCanonical();
|
|
TestRegisters();
|
|
TestNested();
|
|
TestJumpOut();
|
|
TestOtherThread();
|
|
TestWatchedStore();
|
|
for (const int signum : {GUEST_SIGSEGV, GUEST_SIGBUS, GUEST_SIGFPE, GUEST_SIGILL}) Require(sceKernelRemoveExceptionHandler(signum) == 0);
|
|
}
|