Adrià FranchandClaude b0afa04c77 feat(shader): implement basic f64 VALU ops ...

Decode and translate v_add/mul/fma/min/max/ldexp_f64, v_trunc/ceil/floor/
rndne/fract_f64, v_frexp_mant/exp_i32_f64 and the f64 <-> f32/i32/u32
conversions. f64 values stay as their raw bits (U64) in the IR and are
bitcast to double in SPIR-V, which needs the Float64 capability: the
device enables shaderFloat64 when it also preserves signed zero, inf and
NaN for 64-bit floats, and the shader declares SignedZeroInfNanPreserve 64.

Semantics measured on RDNA2 hardware (8209 inputs per op): literals are
the high dword, the 1/(2*pi) inline constant is the exact double,
omod is ignored, clamp maps NaN to +0, min/max quiet a
signaling NaN and drop a quiet one, NaN results are quiet, and the
integer conversions saturate with NaN -> 0. Truncation, rounding and
ldexp are done on the bits so they do not depend on the driver: lavapipe
returned wrong results for f64 RoundEven and Trunc, and GLSL Ldexp is
undefined past +-1024. Fma is NoContraction so RADV keeps it fused.

Co-Authored-By: Claude <[email protected]>

2026-10-04 08:52:14 +02:00

..

Decoder

Merge pull request #227 from adriadam10/feat/png-enc

2026-10-02 22:08:05 +03:00

libs

feat(shader): implement basic f64 VALU ops

2026-10-04 08:52:14 +02:00

relinker

feat(relinker): lower SHA-256 instructions with a memory operand

2026-10-04 08:21:40 +02:00

shader/recompiler

feat(shader): implement basic f64 VALU ops

2026-10-04 08:52:14 +02:00