- v_cndmask_b32: neg/abs on DPP; neg/abs applied on the bits, as the hardware does
- v_mul_legacy_f32: neg/abs on DPP and SDWA, clamp/omod on SDWA and VOP3
- v_ldexp_f16: neg/abs on src0 for VOP3, DPP and SDWA; NaN result chosen on the bits
Co-Authored-By: Claude <[email protected]>
s_cbranch_execz/execnz/vccz/vccnz test the whole wave mask on hardware,
but the single-lane path branched on each lane's own bit, so inactive
lanes took the other side and diverged in scalar state. Branch on a
wave ballot instead, and execute the untested SOPP ops (cdbg branches,
s_clause, s_inst_prefetch, s_setprio, s_waitcnt_depctr, s_ttracedata)
against values measured on hardware.
Co-Authored-By: Claude <[email protected]>
Without fetch-inactive or bound_ctrl, a v_permlane16_b32/v_permlanex16_b32
lane whose source lane is inactive keeps its old value on hardware;
AnyPS5 wrote 0 there. bound_ctrl alone now writes 0.
Co-Authored-By: Claude <[email protected]>
The byte address of each dword of s_buffer_load (soffset + imm + 4*i)
was computed in 32 bits, so a sum past 2^32 wrapped around and read the
start of the buffer. On hardware the sum doesn't wrap: such dwords are
out of range and read 0, like any dword at or past num_records. Both the
bound V# path and the GPU-computed V# path now check the carry.
The new execution test runs s_buffer_load_dwordx4/x16 and
s_load_dwordx16 against values captured on hardware.
Co-Authored-By: Claude <[email protected]>
Preserve each bundled module directory under app0 and resolve Linux dependencies across directories. Add integration coverage for both output formats and Windows startup. Refs #556; duplicate-export rejection remains unchanged.
v_pack_b32_f16 applied neg/abs to bit 31 of the source dword instead of the
selected half. v_cvt_pknorm_{i16,u16}_f32 and v_ldexp_f32 used GLSL
PackSnorm2x16/PackUnorm2x16/Ldexp, which leave NaN, rounding ties and
denormals to the driver. Compute them on the bits as measured on RDNA2.
Co-Authored-By: Claude <[email protected]>
ReadLane counts as a wave-uniform source, so the two-lane wave64 path
shared the first half's gradients with lanes 32 to 63. The test also
runs every case as wave64 with different quads in the upper half.
Co-Authored-By: Claude <[email protected]>
image_sample_cd takes its derivatives in the image_sample_d address
layout; only the hardware LOD selection differs (one LOD per quad instead
of per pixel). The decoder refused it. It now samples with the given
gradients per lane, which matches whenever the lanes of a quad pass equal
derivatives.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
v_ceil/floor/trunc/rndne/fract/sqrt/rsq/rcp/rcp_iflag/log/exp/sin/cos
(f32 and f16) and v_frexp_mant_f32 left NaN, invalid, zero and infinite
results to the driver: signalling NaNs came back unquieted, lavapipe lost
the NaN sign and payload, invalid results were +NaN instead of -NaN, f32
sin/cos at whole and half cycles returned tiny values instead of +0, and
v_fract_f16 of a tiny negative rounded up to 1.0.
Adds an execution test for the 27 opcodes with expected values from
hardware; approximate ops are compared with tolerances from the Vulkan
precision table.
Co-Authored-By: Claude <[email protected]>
writeF16 dropped the clamp bit, so VOP3/SDWA f16 results with clamp
(v_rcp_f16, v_fma_f16, v_cvt_f16_f32, v_add_f16_sdwa, ...) were not
saturated. Clamp now limits to [0, 1] with NaN and -0 going to +0.
The f16 sqrt/rsq/log and sin/cos paths applied omod, which the
hardware ignores on f16 results in the default float mode, and
v_cvt_pkrtz_f16_f32 applied clamp and omod to its inputs, which the
hardware ignores as well.
Co-Authored-By: Claude <[email protected]>
These make up the precise f64 division macro compilers emit for a / b.
Like the f32 ops, the rules were measured on an RDNA2 GPU (41152 rows,
model matches all of them):
- div_scale decides from the exponent fields only: 2^128 or 2^-128
scaling and VCC for differences >= 768 or <= -768, a denormal or huge
(>= 2045) denominator and a numerator exponent <= 53; a NaN source is
passed through unchanged and a zero input gives 0xfff8000000000000.
- div_fmas scales by 2^128 when the exponent of S2 is >= 1024, else
2^-128, before the single rounding, so it reuses the exact fma
emulation with the scale folded into its final rescale.
- div_fixup follows the ISA: NaN sources are quieted, a NaN quotient
with finite inputs becomes +-inf, exponent differences below -1075
give a signed zero.
Co-Authored-By: Claude <[email protected]>
Decode and translate the remaining unary f64 transcendentals and
v_trig_preop_f64.
On RDNA2 hardware v_rcp_f64, v_rsq_f64 and v_sqrt_f64 are approximations
(relative error up to ~2^-24.3 over 8209 inputs; sqrt(1.0) is not even
exact), so they are emitted as exact double operations and the test
compares against the hardware value with a 2^-23 tolerance. Special
cases are exact and selected on bits: NaN inputs are quieted (RADV keeps
signaling NaN on FDiv), negative inputs give the default NaN
0xfff8000000000000, rsq(-0) = -inf, sqrt(-0) = -0.
v_trig_preop_f64 matches the hardware bit for bit on 24627 results plus
a sweep of the table tail: the 2/PI table is 1184 bits (bits below b17
read as zero), shift = 53 * S1[4:0] + max(exp - 1077, 0), +128 scale for
exp >= 1968, omod ignored. The 53-bit window is read from a private u32
table and scaled in two exact steps so only the final multiply rounds.
Stacked on the f64 infrastructure of #446.
Co-Authored-By: Claude <[email protected]>
s_endpgm_saved and s_endpgm_ordered_ps_done end the wave like s_endpgm
(checked on an RDNA2 GPU: nothing after them runs), so they decode to
SEndpgm and the control flow graph treats them as terminators.
s_atc_probe, s_atc_probe_buffer and s_dcache_discard(_x2) have no visible
effect and translate to no-ops like the other scalar cache controls.
s_round_mode is ignored like s_setreg MODE writes; listed in TechnicalDebt.
Co-Authored-By: Claude <[email protected]>
Without bound_ctrl and fetch-inactive, a DPP16 lane whose source lane is
inactive keeps its old value instead of being written with 0. With
fetch-inactive, a source outside the row reads 0.
Co-Authored-By: Claude <[email protected]>
